From: Sasha Levin <sashal@kernel.org>
To: stable@vger.kernel.org
Cc: Pu Lehui <pulehui@huaweicloud.com>, Sasha Levin <sashal@kernel.org>
Subject: Re: [PATCH 5.10 04/14] arm64: insn: Add support for encoding DSB
Date: Sun, 8 Jun 2025 22:34:15 -0400 [thread overview]
Message-ID: <20250608183950-a48a1c0357dc51f9@stable.kernel.org> (raw)
In-Reply-To: <20250607152521.2828291-5-pulehui@huaweicloud.com>
[ Sasha's backport helper bot ]
Hi,
✅ All tests passed successfully. No issues detected.
No action required from the submitter.
The upstream commit SHA1 provided is correct: 63de8abd97ddb9b758bd8f915ecbd18e1f1a87a0
WARNING: Author mismatch between patch and upstream commit:
Backport author: Pu Lehui<pulehui@huaweicloud.com>
Commit author: James Morse<james.morse@arm.com>
Status in newer kernel trees:
6.15.y | Present (exact SHA1)
6.14.y | Present (different SHA1: 1e1963205784)
6.12.y | Present (different SHA1: 2a3915e86187)
6.6.y | Present (different SHA1: 054fc98d691a)
6.1.y | Present (different SHA1: cc0b8e148c33)
5.15.y | Not found
Note: The patch differs from the upstream commit:
---
1: 63de8abd97ddb ! 1: e18103b8fbb3a arm64: insn: Add support for encoding DSB
@@ Metadata
## Commit message ##
arm64: insn: Add support for encoding DSB
+ [ Upstream commit 63de8abd97ddb9b758bd8f915ecbd18e1f1a87a0 ]
+
To generate code in the eBPF epilogue that uses the DSB instruction,
insn.c needs a heler to encode the type and domain.
@@ Commit message
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+ Signed-off-by: Pu Lehui <pulehui@huawei.com>
## arch/arm64/include/asm/insn.h ##
@@ arch/arm64/include/asm/insn.h: u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
@@ arch/arm64/include/asm/insn.h: u32 aarch64_insn_gen_cas(enum aarch64_insn_regist
#endif
u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
+u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type);
- u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
- enum aarch64_insn_system_register sysreg);
+ s32 aarch64_get_branch_offset(u32 insn);
+ u32 aarch64_set_branch_offset(u32 insn, s32 offset);
- ## arch/arm64/lib/insn.c ##
+ ## arch/arm64/kernel/insn.c ##
@@
*
* Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
@@ arch/arm64/lib/insn.c
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/bug.h>
- #include <linux/printk.h>
-@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
+ #include <linux/compiler.h>
+@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
}
@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_extr(enum aarch64_insn_variant varia
insn = aarch64_insn_get_dmb_value();
insn &= ~GENMASK(11, 8);
-@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
+@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
+
return insn;
}
-
++
+u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type)
+{
+ u32 opt, insn;
@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
+
+ return insn;
+}
-+
- u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
- enum aarch64_insn_system_register sysreg)
- {
---
Results of testing on various branches:
| Branch | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-5.15.y | Success | Success |
next prev parent reply other threads:[~2025-06-09 2:34 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-07 15:25 [PATCH 5.10 00/14] backport for CVE-2025-37948 and CVE-2025-37963 Pu Lehui
2025-06-07 15:25 ` [PATCH 5.10 01/14] arm64: insn: Add barrier encodings Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 02/14] arm64: move AARCH64_BREAK_FAULT into insn-def.h Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 03/14] arm64: insn: add encoders for atomic operations Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 04/14] arm64: insn: Add support for encoding DSB Pu Lehui
2025-06-09 2:34 ` Sasha Levin [this message]
2025-06-07 15:25 ` [PATCH 5.10 05/14] arm64: proton-pack: Expose whether the platform is mitigated by firmware Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 06/14] arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 07/14] arm64: errata: Add KRYO 2XX/3XX/4XX silver cores to Spectre BHB safe list Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 08/14] arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 09/14] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 10/14] arm64: proton-pack: Expose whether the branchy loop k value Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 11/14] arm64: spectre: increase parameters that can be used to turn off bhb mitigation individually Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 12/14] arm64: bpf: Add BHB mitigation to the epilogue for cBPF programs Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 13/14] arm64: bpf: Only mitigate cBPF programs loaded by unprivileged users Pu Lehui
2025-06-09 2:34 ` Sasha Levin
2025-06-07 15:25 ` [PATCH 5.10 14/14] arm64: proton-pack: Add new CPUs 'k' values for branch mitigation Pu Lehui
2025-06-09 2:34 ` Sasha Levin
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