[PATCH v2 0/4] PHY LFPS sending configuration fixes

["Jouni Högander" <jouni.hogander@intel.com>]

We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
since we started configuring LFPS sending. According to Bspec Configuring
LFPS sending is needed only when using AUXLess ALPM. This patch avoids
these failures by configuring LFPS sending only when using AUXLess ALPM.

Addition to PHY failure fix this patch set contains some additions
that were seen missing during review:

1. Ensure phy is accessible on lfps configuration
2. Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

Also one optimization is added to avoid unnecessarily calling
intel_cx0_get_owned_lane_mask.

v2:
  - split as a patch set
  - add ensuring phy is accessible on lfps configuration
  - set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

Jouni Högander (4):
  drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM
  drm/i915/display: Avoid unnecessarily calling
    intel_cx0_get_owned_lane_mask
  drm/i915/display: Ensure phy is accessible on lfps configuration
  drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read

 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 22 ++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

-- 
2.43.0