From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: gustavo.sousa@intel.com, "Jouni Högander" <jouni.hogander@intel.com>
Subject: [PATCH v2 1/4] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM
Date: Tue, 22 Jul 2025 13:13:14 +0300 [thread overview]
Message-ID: <20250722101317.1728499-2-jouni.hogander@intel.com> (raw)
In-Reply-To: <20250722101317.1728499-1-jouni.hogander@intel.com>
We are seeing "dmesg-warn/abort - *ERROR* PHY * failed after 3 retries"
since we started configuring LFPS sending. According to Bspec Configuring
LFPS sending is needed only when using AUXLess ALPM. This patch avoids
these failures by configuring LFPS sending only when using AUXLess ALPM.
Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure LFPS sending")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ed8e640b96b0..2b0305bb04cd 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3240,11 +3240,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
{
struct intel_display *display = to_intel_display(encoder);
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
- bool enable = intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
- crtc_state);
int i;
- if (DISPLAY_VER(display) < 20)
+ if (DISPLAY_VER(display) < 20 ||
+ !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
return;
for (i = 0; i < 4; i++) {
@@ -3256,8 +3255,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
CONTROL0_MAC_TRANSMIT_LFPS,
- enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0,
- MB_WRITE_COMMITTED);
+ CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
}
}
--
2.43.0
next prev parent reply other threads:[~2025-07-22 10:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-22 10:13 [PATCH v2 0/4] PHY LFPS sending configuration fixes Jouni Högander
2025-07-22 10:13 ` Jouni Högander [this message]
2025-07-22 11:57 ` [PATCH v2 1/4] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM Gustavo Sousa
2025-07-22 10:13 ` [PATCH v2 2/4] drm/i915/display: Avoid unnecessarily calling intel_cx0_get_owned_lane_mask Jouni Högander
2025-07-22 11:58 ` Gustavo Sousa
2025-07-22 10:13 ` [PATCH v2 3/4] drm/i915/display: Ensure phy is accessible on lfps configuration Jouni Högander
2025-07-22 12:02 ` Gustavo Sousa
2025-07-22 10:13 ` [PATCH v2 4/4] drm/i915/display: Set C10_VDR_CTRL_MSGBUS_ACCESS before phy reg read Jouni Högander
2025-07-22 12:07 ` Gustavo Sousa
2025-07-22 12:14 ` Hogander, Jouni
2025-07-22 10:31 ` ✓ CI.KUnit: success for PHY LFPS sending configuration fixes Patchwork
2025-07-22 11:07 ` ✓ i915.CI.BAT: " Patchwork
2025-07-22 11:53 ` ✓ Xe.CI.BAT: " Patchwork
2025-07-22 13:32 ` ✗ Xe.CI.Full: failure " Patchwork
2025-07-22 14:09 ` ✗ i915.CI.Full: " Patchwork
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