Re: [PATCH v8 01/11] cxl: Add helper to detect top of CXL device topology

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Thu, 14 Aug 2025 15:21:41 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Add a helper to replace the open code detection of CXL device hierarchy
> root, or the host bridge. The helper will be used for delayed downstream
> port (dport) creation.
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Li Ming <ming.li@zohomail.com>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v8:
> - Rename to is_cxl_host_bridge() (Dan)
> - Rename duplicate tags from Jonathan
> ---
>  drivers/cxl/core/port.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 29197376b18e..855623cebd7d 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -33,6 +33,15 @@
>  static DEFINE_IDA(cxl_port_ida);
>  static DEFINE_XARRAY(cxl_root_buses);
>  
> +/*
> + * The terminal device in PCI is NULL and @platform_bus
> + * for platform devices (for cxl_test)

Silly but it tickled my in built line length detector...

* The terminal device in PCI is NULL and @platform_bus for platform devices 
* (for cxl_test)

Obviously makes to practical difference to anything!


> + */
> +static bool is_cxl_host_bridge(struct device *dev)
> +{
> +	return (!dev || dev == &platform_bus);
> +}
> +
>  int cxl_num_decoders_committed(struct cxl_port *port)
>  {
>  	lockdep_assert_held(&cxl_rwsem.region);
> @@ -1541,7 +1550,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
>  	resource_size_t component_reg_phys;
>  	int rc;
>  
> -	if (!dparent) {
> +	if (is_cxl_host_bridge(dparent)) {
>  		/*
>  		 * The iteration reached the topology root without finding the
>  		 * CXL-root 'cxl_port' on a previous iteration, fail for now to
> @@ -1629,11 +1638,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
>  		struct device *uport_dev;
>  		struct cxl_dport *dport;
>  
> -		/*
> -		 * The terminal "grandparent" in PCI is NULL and @platform_bus
> -		 * for platform devices
> -		 */
> -		if (!dport_dev || dport_dev == &platform_bus)
> +		if (is_cxl_host_bridge(dport_dev))
>  			return 0;
>  
>  		uport_dev = dport_dev->parent;