Re: [PATCH v8 04/11] cxl: Move port register setup to first dport appear

[Jonathan Cameron <Jonathan.Cameron@huawei.com>]

On Thu, 14 Aug 2025 15:21:44 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> This patch moves the port register setup to when the first dport appears
> via the memdev probe path. At this point, the CXL link should be
> established and the register access is expected to succeed. This change
> addresses an error message observed when PCIe hotplug is enabled on
> an Intel platform. The error messages "cxl portN: Couldn't locate the
> CXL.cache and CXL.mem capability array header" is observed for the
> hostbridge during cxl_acpi driver probe. If the cxl_acpi module
> probe is running before the CXL link between the endpoint device and the
> RP is established, then the platform may not have exposed DVSEC ID 3
> and/or DVSEC ID 7 blocks which will trigger the error message. This
> behavior is defined by the spec and not a hardware quirk.
> 
> This change also needs the dport enumeration to be moved to the memdev
> probe path in order to address the issue. This change is just part of
> the code refactoring and is not a wholly contained fix itself.
> 
> Suggested-by: Dan Williamsn <dan.j.williams@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
I'm a little nervous about what happens when we hot unplug EPs
on these systems and any left over address mappings for port to which
they are connected.  But from previous discussions I think the argument
was that they were benign if they do happen.

Anyhow, this looks fine to me.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>