From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dave@stgolabs.net>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<rrichter@amd.com>
Subject: Re: [PATCH v8 11/11] tools/testing/cxl: Add decoder save/restore support
Date: Fri, 15 Aug 2025 14:15:21 +0100 [thread overview]
Message-ID: <20250815141521.00003992@huawei.com> (raw)
In-Reply-To: <20250814222151.3520500-12-dave.jiang@intel.com>
On Thu, 14 Aug 2025 15:21:51 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> Record decoder values at init and mock_decoder_commit() time, and
> restore them at the next invocation of mock_init_hdm_decoder(). Add 2
> attributes to the cxl_test "cxl_acpi" device to optionally flush the
> cache of topology decoder values, or disable updating the decoder at
> mock_decoder_reset() time.
>
> This enables replaying a saved decoder configuration when re-triggering
> a topology scan by re-binding the cxl_acpi driver to "cxl_acpi.0" (the
> cxl_test emulation of an ACPI0017 instance).
>
> # modprobe cxl_test
> # cxl list -RB -b cxl_test -u
> {
> "bus":"root3",
> "provider":"cxl_test",
> "regions:root3":[
> {
> "region":"region5",
> "resource":"0xf010000000",
> "size":"512.00 MiB (536.87 MB)",
> "type":"ram",
> "interleave_ways":2,
> "interleave_granularity":4096,
> "decode_state":"commit"
> }
> ]
> }
> # echo 1 > /sys/bus/platform/devices/cxl_acpi.0/decoder_registry_reset_disable
> # echo cxl_acpi.0 > /sys/bus/platform/drivers/cxl_acpi/unbind
> # cxl list -RB -b cxl_test -u
> # echo cxl_acpi.0 > /sys/bus/platform/drivers/cxl_acpi/bind
> # cxl list -RB -b cxl_test -u
> {
> "bus":"root3",
> "provider":"cxl_test",
> "regions:root3":[
> {
> "region":"region5",
> "resource":"0xf010000000",
> "size":"512.00 MiB (536.87 MB)",
> "type":"ram",
> "interleave_ways":2,
> "interleave_granularity":4096,
> "decode_state":"commit"
> }
> ]
> }
>
> [dj: Added support for delayed dport initialization ]
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Authorship wrong, or a Co-dev missing? Was expecting to see a From: Dan...
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> - Will have a cxl-replay test script in CXL CLI package
> - This allowed me to test assembly and replay for manually created CXL regions
> ---
> tools/testing/cxl/test/cxl.c | 300 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 298 insertions(+), 2 deletions(-)
>
> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
> index 2d50193d10fe..e0da2a48d2a8 100644
> --- a/tools/testing/cxl/test/cxl.c
> +++ b/tools/testing/cxl/test/cxl.c
> @@ -47,6 +47,9 @@ struct platform_device *cxl_mem_single[NR_MEM_SINGLE];
> static struct platform_device *cxl_rch[NR_CXL_RCH];
> static struct platform_device *cxl_rcd[NR_CXL_RCH];
>
> +static DEFINE_XARRAY(decoder_registry);
> +static bool decoder_registry_reset_disable;
> +
> static inline bool is_multi_bridge(struct device *dev)
> {
> int i;
> @@ -671,6 +674,164 @@ static int map_targets(struct device *dev, void *data)
> return 0;
> }
>
> +static unsigned long cxld_registry_index(struct cxl_decoder *cxld)
> +{
> + struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> +
> + /*
> + * Upper nibble of a kernel pointer is 0xff, chop that to make
Very unlikely a nibble is 0xff, more likely 0xf unless you x86 folk have
8 bit nibbles :)
> + * space for a cxl_decoder id which should be less than 128
> + * given decoder count is a 4-bit field.
If it's a 4 bit field, how can it be greater than 15?
Maybe I need more coffee.
> + *
> + * While @port is reallocated each enumeration, @port->uport_dev
> + * is stable.
> + */
> + dev_WARN_ONCE(&port->dev, cxld->id >= 128,
> + "decoder id:%d out of range\n", cxld->id);
> + return (((unsigned long) port->uport_dev) << 4) | cxld->id;
> +}
next prev parent reply other threads:[~2025-08-15 13:15 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-14 22:21 [PATCH v8 00/11] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-08-14 22:21 ` [PATCH v8 01/11] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-08-15 12:50 ` Jonathan Cameron
2025-08-20 13:51 ` Robert Richter
2025-08-14 22:21 ` [PATCH v8 02/11] cxl: Add helper to reap dport Dave Jiang
2025-08-20 14:10 ` Robert Richter
2025-08-20 20:54 ` Dave Jiang
2025-08-14 22:21 ` [PATCH v8 03/11] cxl: Add a cached copy of target_map to cxl_decoder Dave Jiang
2025-08-15 12:52 ` Jonathan Cameron
2025-08-20 14:17 ` Robert Richter
2025-08-14 22:21 ` [PATCH v8 04/11] cxl: Move port register setup to first dport appear Dave Jiang
2025-08-15 12:57 ` Jonathan Cameron
2025-08-21 11:57 ` Robert Richter
2025-08-22 10:37 ` Robert Richter
2025-08-14 22:21 ` [PATCH v8 05/11] cxl: Defer dport allocation for switch ports Dave Jiang
2025-08-20 12:41 ` Robert Richter
2025-08-20 15:20 ` Dave Jiang
2025-08-22 9:59 ` Robert Richter
2025-08-22 15:52 ` Dave Jiang
2025-08-26 7:51 ` Robert Richter
2025-08-27 17:05 ` Dave Jiang
2025-08-29 15:02 ` Robert Richter
2025-08-29 17:23 ` Dave Jiang
2025-09-01 14:48 ` Robert Richter
2025-09-02 15:58 ` Dave Jiang
2025-08-27 21:15 ` Dave Jiang
2025-09-01 17:29 ` Robert Richter
2025-09-02 15:40 ` Dave Jiang
2025-09-03 18:21 ` Dave Jiang
2025-08-27 21:37 ` Dave Jiang
2025-08-14 22:21 ` [PATCH v8 06/11] cxl/test: Add cxl_test support for cxl_port_get_possible_dports() Dave Jiang
2025-08-14 22:21 ` [PATCH v8 07/11] cxl/test: Add mock version of devm_cxl_add_dport_by_dev() Dave Jiang
2025-08-14 22:21 ` [PATCH v8 08/11] cxl/test: Add support to cxl_test for decoder enumeration mock functions Dave Jiang
2025-08-14 22:21 ` [PATCH v8 09/11] cxl/test: Setup target_map for cxl_test decoder initialization Dave Jiang
2025-08-15 13:04 ` Jonathan Cameron
2025-08-14 22:21 ` [PATCH v8 10/11] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-08-14 22:21 ` [PATCH v8 11/11] tools/testing/cxl: Add decoder save/restore support Dave Jiang
2025-08-15 13:15 ` Jonathan Cameron [this message]
2025-08-19 9:39 ` [PATCH v8 00/11] cxl: Delay HB port and switch dport probing until endpoint dev probe Robert Richter
2025-08-19 15:41 ` Dave Jiang
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