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From: kernel test robot <lkp@intel.com>
To: hans.zhang@cixtech.com, bhelgaas@google.com, helgaas@kernel.org,
	lpieralisi@kernel.org, kw@linux.com, mani@kernel.org,
	robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org
Cc: oe-kbuild-all@lists.linux.dev, mpillai@cadence.com,
	fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
	peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v11 03/10] PCI: cadence: Move PCIe RP common functions to a separate file
Date: Sun, 9 Nov 2025 21:59:50 +0800	[thread overview]
Message-ID: <202511092106.mkNV0iyb-lkp@intel.com> (raw)
In-Reply-To: <20251108140305.1120117-4-hans.zhang@cixtech.com>

Hi,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 6146a0f1dfae5d37442a9ddcba012add260bceb0]

url:    https://github.com/intel-lab-lkp/linux/commits/hans-zhang-cixtech-com/PCI-cadence-Add-module-support-for-platform-controller-driver/20251108-220607
base:   6146a0f1dfae5d37442a9ddcba012add260bceb0
patch link:    https://lore.kernel.org/r/20251108140305.1120117-4-hans.zhang%40cixtech.com
patch subject: [PATCH v11 03/10] PCI: cadence: Move PCIe RP common functions to a separate file
config: i386-randconfig-014-20251109 (https://download.01.org/0day-ci/archive/20251109/202511092106.mkNV0iyb-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251109/202511092106.mkNV0iyb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511092106.mkNV0iyb-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/pci/controller/cadence/pcie-cadence-host-common.c: In function 'cdns_pcie_host_bar_config':
>> drivers/pci/controller/cadence/pcie-cadence-host-common.c:188:23: warning: variable 'pci_addr' set but not used [-Wunused-but-set-variable]
     188 |         u64 cpu_addr, pci_addr, size, winsize;
         |                       ^~~~~~~~


vim +/pci_addr +188 drivers/pci/controller/cadence/pcie-cadence-host-common.c

   183	
   184	int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
   185				      struct resource_entry *entry,
   186				      cdns_pcie_host_bar_ib_cfg pci_host_ib_config)
   187	{
 > 188		u64 cpu_addr, pci_addr, size, winsize;
   189		struct cdns_pcie *pcie = &rc->pcie;
   190		struct device *dev = pcie->dev;
   191		enum cdns_pcie_rp_bar bar;
   192		unsigned long flags;
   193		int ret;
   194	
   195		cpu_addr = entry->res->start;
   196		pci_addr = entry->res->start - entry->offset;
   197		flags = entry->res->flags;
   198		size = resource_size(entry->res);
   199	
   200		while (size > 0) {
   201			/*
   202			 * Try to find a minimum BAR whose size is greater than
   203			 * or equal to the remaining resource_entry size. This will
   204			 * fail if the size of each of the available BARs is less than
   205			 * the remaining resource_entry size.
   206			 *
   207			 * If a minimum BAR is found, IB ATU will be configured and
   208			 * exited.
   209			 */
   210			bar = cdns_pcie_host_find_min_bar(rc, size);
   211			if (bar != RP_BAR_UNDEFINED) {
   212				ret = pci_host_ib_config(rc, bar, cpu_addr, size, flags);
   213				if (ret)
   214					dev_err(dev, "IB BAR: %d config failed\n", bar);
   215				return ret;
   216			}
   217	
   218			/*
   219			 * If the control reaches here, it would mean the remaining
   220			 * resource_entry size cannot be fitted in a single BAR. So we
   221			 * find a maximum BAR whose size is less than or equal to the
   222			 * remaining resource_entry size and split the resource entry
   223			 * so that part of resource entry is fitted inside the maximum
   224			 * BAR. The remaining size would be fitted during the next
   225			 * iteration of the loop.
   226			 *
   227			 * If a maximum BAR is not found, there is no way we can fit
   228			 * this resource_entry, so we error out.
   229			 */
   230			bar = cdns_pcie_host_find_max_bar(rc, size);
   231			if (bar == RP_BAR_UNDEFINED) {
   232				dev_err(dev, "No free BAR to map cpu_addr %llx\n",
   233					cpu_addr);
   234				return -EINVAL;
   235			}
   236	
   237			winsize = bar_max_size[bar];
   238			ret = pci_host_ib_config(rc, bar, cpu_addr, winsize, flags);
   239			if (ret) {
   240				dev_err(dev, "IB BAR: %d config failed\n", bar);
   241				return ret;
   242			}
   243	
   244			size -= winsize;
   245			cpu_addr += winsize;
   246		}
   247	
   248		return 0;
   249	}
   250	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

  reply	other threads:[~2025-11-09 14:00 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-08 14:02 [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-11-08 14:02 ` [PATCH v11 01/10] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-11-08 14:02 ` [PATCH v11 02/10] PCI: cadence: Split PCIe controller header file hans.zhang
2025-11-08 14:02 ` [PATCH v11 03/10] PCI: cadence: Move PCIe RP common functions to a separate file hans.zhang
2025-11-09 13:59   ` kernel test robot [this message]
2025-11-09 17:01     ` Manivannan Sadhasivam
2025-11-10  1:25       ` Hans Zhang
2025-11-08 14:02 ` [PATCH v11 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-11-17 21:08   ` Bjorn Helgaas
2025-11-18  0:45     ` Hans Zhang
2025-11-08 14:03 ` [PATCH v11 05/10] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-11-08 14:03 ` [PATCH v11 06/10] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-11-08 14:03 ` [PATCH v11 07/10] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-11-08 14:03 ` [PATCH v11 08/10] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-11-08 14:03 ` [PATCH v11 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-11-14 17:40   ` Manivannan Sadhasivam
2025-11-17  9:31   ` Peter Chen
2025-11-08 14:03 ` [PATCH v11 10/10] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-11-14 17:41   ` Manivannan Sadhasivam
2025-11-17  9:31   ` Peter Chen
2025-11-14 17:38 ` (subset) [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam

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