From: Hans Zhang <hans.zhang@cixtech.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com,
fugang.duan@cixtech.com, guoyin.chen@cixtech.com,
peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v11 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller
Date: Tue, 18 Nov 2025 08:45:09 +0800 [thread overview]
Message-ID: <52abaad8-a43e-4e29-93d7-86a3245692c3@cixtech.com> (raw)
In-Reply-To: <20251117210805.GA2531096@bhelgaas>
On 11/18/2025 5:08 AM, Bjorn Helgaas wrote:
> EXTERNAL EMAIL
>
> On Sat, Nov 08, 2025 at 10:02:59PM +0800, hans.zhang@cixtech.com wrote:
>> From: Manikandan K Pillai <mpillai@cadence.com>
>>
>> Add support for Cadence PCIe RP configuration for High Performance
>> Architecture (HPA) controllers. The Cadence High Performance
>> controllers are the latest PCIe controllers that have support for DMA,
>> optional IDE and updated register set. Add register definitions for High
>> Performance Architecture (HPA) PCIe controllers.
>
>> /**
>> * struct cdns_pcie - private data for Cadence PCIe controller drivers
>> * @reg_base: IO mapped register base
>> * @mem_res: start/end offsets in the physical system memory to map PCI accesses
>> + * @msg_res: Region for send message to map PCI accesses
>> * @dev: PCIe controller
>> * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
>> * @phy_count: number of supported PHY devices
>> @@ -45,16 +85,20 @@ struct cdns_pcie_ops {
>> * @link: list of pointers to corresponding device link representations
>> * @ops: Platform-specific ops to control various inputs from Cadence PCIe
>> * wrapper
>> + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
>> */
>> struct cdns_pcie {
>> - void __iomem *reg_base;
>> - struct resource *mem_res;
>> - struct device *dev;
>> - bool is_rc;
>> - int phy_count;
>> - struct phy **phy;
>> - struct device_link **link;
>> - const struct cdns_pcie_ops *ops;
>> + void __iomem *reg_base;
>> + void __iomem *mem_base;
>
> $ DIR=drivers/pci/
> $ find $DIR -type f -name \*.[ch] | xargs scripts/kernel-doc -none 2>&1
> Warning: drivers/pci/controller/cadence/pcie-cadence.h:101 struct member 'mem_base' not described in 'cdns_pcie'
>
> Can you supply text for this doc? We can amend the commit to include
> it.
Hi Bjorn,
This variable should be deleted. Mani, could you please help handle it?
It seems that Manikandan missed deleting this variable during the
modification process. I checked and found that it wasn't used.
Best regards,
Hans
next prev parent reply other threads:[~2025-11-18 0:45 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-08 14:02 [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-11-08 14:02 ` [PATCH v11 01/10] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-11-08 14:02 ` [PATCH v11 02/10] PCI: cadence: Split PCIe controller header file hans.zhang
2025-11-08 14:02 ` [PATCH v11 03/10] PCI: cadence: Move PCIe RP common functions to a separate file hans.zhang
2025-11-09 13:59 ` kernel test robot
2025-11-09 17:01 ` Manivannan Sadhasivam
2025-11-10 1:25 ` Hans Zhang
2025-11-08 14:02 ` [PATCH v11 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-11-17 21:08 ` Bjorn Helgaas
2025-11-18 0:45 ` Hans Zhang [this message]
2025-11-08 14:03 ` [PATCH v11 05/10] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-11-08 14:03 ` [PATCH v11 06/10] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-11-08 14:03 ` [PATCH v11 07/10] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-11-08 14:03 ` [PATCH v11 08/10] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-11-08 14:03 ` [PATCH v11 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-11-14 17:40 ` Manivannan Sadhasivam
2025-11-17 9:31 ` Peter Chen
2025-11-08 14:03 ` [PATCH v11 10/10] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-11-14 17:41 ` Manivannan Sadhasivam
2025-11-17 9:31 ` Peter Chen
2025-11-14 17:38 ` (subset) [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam
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