From: Peter Chen <peter.chen@cixtech.com>
To: hans.zhang@cixtech.com
Cc: <bhelgaas@google.com>, <helgaas@kernel.org>,
<lpieralisi@kernel.org>, <kw@linux.com>, <mani@kernel.org>,
<robh@kernel.org>, <kwilczynski@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <mpillai@cadence.com>,
<fugang.duan@cixtech.com>, <guoyin.chen@cixtech.com>,
<cix-kernel-upstream@cixtech.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v11 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1
Date: Mon, 17 Nov 2025 17:31:14 +0800 [thread overview]
Message-ID: <aRrrYm-cYTUmUPHI@nchen-desktop> (raw)
In-Reply-To: <20251108140305.1120117-10-hans.zhang@cixtech.com>
On 25-11-08 22:03:04, hans.zhang@cixtech.com wrote:
> From: Hans Zhang <hans.zhang@cixtech.com>
Applied, Thanks.
Peter
>
> Add pcie_x*_rc node to support Sky1 PCIe driver based on the
> Cadence PCIe core.
>
> Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts
> using the ARM GICv3.
>
> Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
> ---
> arch/arm64/boot/dts/cix/sky1.dtsi | 126 ++++++++++++++++++++++++++++++
> 1 file changed, 126 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index 2fb2c99c0796..1abafbfc3c9b 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -388,6 +388,132 @@ mbox_ap2sfh: mailbox@80a0000 {
> cix,mbox-dir = "tx";
> };
>
> + pcie_x8_rc: pcie@a010000 {
> + compatible = "cix,sky1-pcie-host";
> + reg = <0x00 0x0a010000 0x00 0x10000>,
> + <0x00 0x2c000000 0x00 0x4000000>,
> + <0x00 0x0a000300 0x00 0x100>,
> + <0x00 0x0a000400 0x00 0x100>,
> + <0x00 0x60000000 0x00 0x00100000>;
> + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> + ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>,
> + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>,
> + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0xc0 0xff>;
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
> + msi-map = <0xc000 &gic_its 0xc000 0x4000>;
> + status = "disabled";
> + };
> +
> + pcie_x4_rc: pcie@a070000 {
> + compatible = "cix,sky1-pcie-host";
> + reg = <0x00 0x0a070000 0x00 0x10000>,
> + <0x00 0x29000000 0x00 0x3000000>,
> + <0x00 0x0a060300 0x00 0x40>,
> + <0x00 0x0a060400 0x00 0x40>,
> + <0x00 0x50000000 0x00 0x00100000>;
> + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> + ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>,
> + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>,
> + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x90 0xbf>;
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>;
> + msi-map = <0x9000 &gic_its 0x9000 0x3000>;
> + status = "disabled";
> + };
> +
> + pcie_x2_rc: pcie@a0c0000 {
> + compatible = "cix,sky1-pcie-host";
> + reg = <0x00 0x0a0c0000 0x00 0x10000>,
> + <0x00 0x26000000 0x00 0x3000000>,
> + <0x00 0x0a0600340 0x00 0x20>,
> + <0x00 0x0a0600440 0x00 0x20>,
> + <0x00 0x40000000 0x00 0x00100000>;
> + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> + ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>,
> + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>,
> + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x60 0x8f>;
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>;
> + msi-map = <0x6000 &gic_its 0x6000 0x3000>;
> + status = "disabled";
> + };
> +
> + pcie_x1_0_rc: pcie@a0d0000 {
> + compatible = "cix,sky1-pcie-host";
> + reg = <0x00 0x0a0d0000 0x00 0x10000>,
> + <0x00 0x20000000 0x00 0x3000000>,
> + <0x00 0x0a060360 0x00 0x20>,
> + <0x00 0x0a060460 0x00 0x20>,
> + <0x00 0x30000000 0x00 0x00100000>;
> + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> + ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>,
> + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>,
> + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0x2f>;
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>;
> + msi-map = <0x0000 &gic_its 0x0000 0x3000>;
> + status = "disabled";
> + };
> +
> + pcie_x1_1_rc: pcie@a0e0000 {
> + compatible = "cix,sky1-pcie-host";
> + reg = <0x00 0x0a0e0000 0x00 0x10000>,
> + <0x00 0x23000000 0x00 0x3000000>,
> + <0x00 0x0a060380 0x00 0x20>,
> + <0x00 0x0a060480 0x00 0x20>,
> + <0x00 0x38000000 0x00 0x00100000>;
> + reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
> + ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>,
> + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>,
> + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x30 0x5f>;
> + device_type = "pci";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>,
> + <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>;
> + msi-map = <0x3000 &gic_its 0x3000 0x3000>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@e010000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x0e010000 0 0x10000>, /* GICD */
> --
> 2.49.0
>
--
Best regards,
Peter
next prev parent reply other threads:[~2025-11-17 9:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-08 14:02 [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-11-08 14:02 ` [PATCH v11 01/10] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-11-08 14:02 ` [PATCH v11 02/10] PCI: cadence: Split PCIe controller header file hans.zhang
2025-11-08 14:02 ` [PATCH v11 03/10] PCI: cadence: Move PCIe RP common functions to a separate file hans.zhang
2025-11-09 13:59 ` kernel test robot
2025-11-09 17:01 ` Manivannan Sadhasivam
2025-11-10 1:25 ` Hans Zhang
2025-11-08 14:02 ` [PATCH v11 04/10] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-11-17 21:08 ` Bjorn Helgaas
2025-11-18 0:45 ` Hans Zhang
2025-11-08 14:03 ` [PATCH v11 05/10] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-11-08 14:03 ` [PATCH v11 06/10] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-11-08 14:03 ` [PATCH v11 07/10] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-11-08 14:03 ` [PATCH v11 08/10] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-11-08 14:03 ` [PATCH v11 09/10] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-11-14 17:40 ` Manivannan Sadhasivam
2025-11-17 9:31 ` Peter Chen [this message]
2025-11-08 14:03 ` [PATCH v11 10/10] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-11-14 17:41 ` Manivannan Sadhasivam
2025-11-17 9:31 ` Peter Chen
2025-11-14 17:38 ` (subset) [PATCH v11 00/10] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam
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