* [PATCH v1 00/11] Add SSP/TSP power control and DRAM remap support for AST2700
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This series improves AST2700 platform support by aligning SSP/TSP
power and reset behavior with hardware, and enabling DRAM remapping
required for proper firmware boot flow.
v1:
1. The changes move DRAM/SDMC initialization earlier to support memory
aliasing, add DRAM aliases for SSP/TSP SDRAM remap, and implement
SSP/TSP reset, power-on, and remap controls via SCU registers.
2. With these updates, SSP and TSP can be booted via PSP and load their
binaries from DRAM. Functional tests and documentation are updated
accordingly.
Jamin Lin (11):
hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support
memory aliasing
hw/arm/ast27x0: Start SSP in powered-off state to match hardware
behavior
hw/arm/ast27x0: Start TSP in powered-off state to match hardware
behavior
hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU
registers
hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU
registers
hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
and load binaries from DRAM
docs: Add support vbootrom and update Manual boot for ast2700fc
docs/system/arm/aspeed.rst | 37 ++-
include/hw/misc/aspeed_scu.h | 6 +
hw/arm/aspeed_ast27x0-fc.c | 4 +
hw/arm/aspeed_ast27x0-ssp.c | 13 +
hw/arm/aspeed_ast27x0-tsp.c | 10 +
hw/arm/aspeed_ast27x0.c | 46 +--
hw/misc/aspeed_scu.c | 268 +++++++++++++++++-
.../aarch64/test_aspeed_ast2700fc.py | 35 ++-
8 files changed, 378 insertions(+), 41 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v1 00/11] Add SSP/TSP power control and DRAM remap support for AST2700
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This series improves AST2700 platform support by aligning SSP/TSP
power and reset behavior with hardware, and enabling DRAM remapping
required for proper firmware boot flow.
v1:
1. The changes move DRAM/SDMC initialization earlier to support memory
aliasing, add DRAM aliases for SSP/TSP SDRAM remap, and implement
SSP/TSP reset, power-on, and remap controls via SCU registers.
2. With these updates, SSP and TSP can be booted via PSP and load their
binaries from DRAM. Functional tests and documentation are updated
accordingly.
Jamin Lin (11):
hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support
memory aliasing
hw/arm/ast27x0: Start SSP in powered-off state to match hardware
behavior
hw/arm/ast27x0: Start TSP in powered-off state to match hardware
behavior
hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU
registers
hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU
registers
hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP
and load binaries from DRAM
docs: Add support vbootrom and update Manual boot for ast2700fc
docs/system/arm/aspeed.rst | 37 ++-
include/hw/misc/aspeed_scu.h | 6 +
hw/arm/aspeed_ast27x0-fc.c | 4 +
hw/arm/aspeed_ast27x0-ssp.c | 13 +
hw/arm/aspeed_ast27x0-tsp.c | 10 +
hw/arm/aspeed_ast27x0.c | 46 +--
hw/misc/aspeed_scu.c | 268 +++++++++++++++++-
.../aarch64/test_aspeed_ast2700fc.py | 35 ++-
8 files changed, 378 insertions(+), 41 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v1 01/11] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the
initialization of the SDMC (SDRAM controller) and DRAM models earlier in
the device realization order.
In the upcoming changes, the PSP will expose a portion of its DRAM as shared
memory by creating a memory region alias at a specific offset. This alias is
mapped into the coprocessor's SDRAM address space, allowing both PSP and the
coprocessor (SSP/TSP) to access the same physical memory through their respective
views — PSP via its DRAM, and the coprocessor via its SDRAM.
The remapping is configured through SCU registers and enables shared memory
communication between PSP and the coprocessors.
Therefore, the DRAM and SDMC devices must be realized before:
- the SCU, which configures the alias offset and size
- the coprocessors, which access the alias through their SDRAM window
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d17f446661..74a004adca 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -702,6 +702,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
+ /*
+ * SDMC - SDRAM Memory Controller
+ * The SDMC controller is unlocked at SPL stage.
+ * At present, only supports to emulate booting
+ * start from u-boot stage. Set SDMC controller
+ * unlocked by default. It is a temporarily solution.
+ */
+ object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
+ sc->memmap[ASPEED_DEV_SDMC]);
+
+ /* RAM */
+ if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
+ return;
+ }
+
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
@@ -792,26 +812,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
ASPEED_DEV_EHCI1 + i));
}
- /*
- * SDMC - SDRAM Memory Controller
- * The SDMC controller is unlocked at SPL stage.
- * At present, only supports to emulate booting
- * start from u-boot stage. Set SDMC controller
- * unlocked by default. It is a temporarily solution.
- */
- object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
- sc->memmap[ASPEED_DEV_SDMC]);
-
- /* RAM */
- if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
- return;
- }
-
/* Net */
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 01/11] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the
initialization of the SDMC (SDRAM controller) and DRAM models earlier in
the device realization order.
In the upcoming changes, the PSP will expose a portion of its DRAM as shared
memory by creating a memory region alias at a specific offset. This alias is
mapped into the coprocessor's SDRAM address space, allowing both PSP and the
coprocessor (SSP/TSP) to access the same physical memory through their respective
views — PSP via its DRAM, and the coprocessor via its SDRAM.
The remapping is configured through SCU registers and enables shared memory
communication between PSP and the coprocessors.
Therefore, the DRAM and SDMC devices must be realized before:
- the SCU, which configures the alias offset and size
- the coprocessors, which access the alias through their SDRAM window
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index d17f446661..74a004adca 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -702,6 +702,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
+ /*
+ * SDMC - SDRAM Memory Controller
+ * The SDMC controller is unlocked at SPL stage.
+ * At present, only supports to emulate booting
+ * start from u-boot stage. Set SDMC controller
+ * unlocked by default. It is a temporarily solution.
+ */
+ object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
+ sc->memmap[ASPEED_DEV_SDMC]);
+
+ /* RAM */
+ if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
+ return;
+ }
+
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
@@ -792,26 +812,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
ASPEED_DEV_EHCI1 + i));
}
- /*
- * SDMC - SDRAM Memory Controller
- * The SDMC controller is unlocked at SPL stage.
- * At present, only supports to emulate booting
- * start from u-boot stage. Set SDMC controller
- * unlocked by default. It is a temporarily solution.
- */
- object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sdmc), 0,
- sc->memmap[ASPEED_DEV_SDMC]);
-
- /* RAM */
- if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
- return;
- }
-
/* Net */
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then releasing
the SSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the SSP's ARMv7M core. This change ensures
the SSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls SSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cee937b37e..cba59ae11a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then releasing
the SSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the SSP's ARMv7M core. This change ensures
the SSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls SSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cee937b37e..cba59ae11a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 03/11] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then releasing
the TSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the TSP's ARMv7M core. This change ensures
the TSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls TSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9c11c016ca..46691080d1 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The TSP starts in a powered-down state and can be powered up
+ * by setting the TSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 03/11] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then releasing
the TSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the TSP's ARMv7M core. This change ensures
the TSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls TSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9c11c016ca..46691080d1 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -165,6 +165,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The TSP starts in a powered-down state and can be powered up
+ * by setting the TSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The SSP exposes two DRAM aliases:
- remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000
- remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0
These regions correspond to the default SCU register values, which control
the mapping between PSP and coprocessor memory windows.
Set SSP CPUID 4 and bumps the SCU VMState version to 3.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 5 +++++
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
hw/arm/aspeed_ast27x0.c | 4 ++++
hw/misc/aspeed_scu.c | 38 ++++++++++++++++++++++++++++++++++--
5 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 9e28bd4d2e..6f7f7d2766 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -39,6 +39,10 @@ struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
+
+ MemoryRegion dram_remap_alias[3];
+ MemoryRegion *dram;
+ int ssp_cpuid;
};
#define AST2400_A0_SILICON_REV 0x02000303U
@@ -73,6 +77,7 @@ struct AspeedSCUClass {
uint32_t nr_regs;
bool clkin_25Mhz;
const MemoryRegionOps *ops;
+ void (*dram_remap)(AspeedSCUState *s);
};
#define ASPEED_SCU_PROT_KEY 0x1688A8A8
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 0502a137f3..b788e6ca2a 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -101,6 +101,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
+ object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cba59ae11a..cf1339e2c7 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -198,6 +198,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
+ /* SDRAM remap alias used by PSP to access SSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&s->scu->dram_remap_alias[1]),
+ &s->scu->dram_remap_alias[0]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 74a004adca..ae8b22fc1c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -389,6 +389,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-strap1");
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
+ object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu),
+ "ssp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
@@ -740,6 +742,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
/* SCU */
+ object_property_set_link(OBJECT(&s->scu), "dram", OBJECT(s->dram_mr),
+ &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6829efa2dc..4b74e5adcb 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "qemu/units.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -602,12 +603,20 @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp)
TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+
+ if (asc->dram_remap) {
+ if (!s->dram) {
+ error_setg(errp, TYPE_ASPEED_SCU ": 'dram' link not set");
+ return;
+ }
+ asc->dram_remap(s);
+ }
}
static const VMStateDescription vmstate_aspeed_scu = {
.name = "aspeed.scu",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
VMSTATE_END_OF_LIST()
@@ -619,6 +628,9 @@ static const Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
+ DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1),
+ DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
};
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
@@ -872,6 +884,27 @@ static const TypeInfo aspeed_2600_scu_info = {
.class_init = aspeed_2600_scu_class_init,
};
+static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
+{
+ if (s->ssp_cpuid > 0) {
+ /*
+ * The SSP coprocessor uses two memory aliases (remap1 and remap2)
+ * to access shared memory regions in the PSP DRAM:
+ *
+ * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM
+ * offset 0x2000000
+ * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM
+ * offset 0x0
+ */
+ memory_region_init_alias(&s->dram_remap_alias[0], OBJECT(s),
+ "ssp.dram.remap1", s->dram,
+ 0, 32 * MiB);
+ memory_region_init_alias(&s->dram_remap_alias[1], OBJECT(s),
+ "ssp.dram.remap2", s->dram,
+ 0x2c000000, 32 * MiB);
+ }
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -982,6 +1015,7 @@ static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
asc->clkin_25Mhz = true;
asc->ops = &aspeed_ast2700_scu_ops;
+ asc->dram_remap = aspeed_2700_scu_dram_remap_alias_init;
}
static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The SSP exposes two DRAM aliases:
- remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000
- remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0
These regions correspond to the default SCU register values, which control
the mapping between PSP and coprocessor memory windows.
Set SSP CPUID 4 and bumps the SCU VMState version to 3.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 5 +++++
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
hw/arm/aspeed_ast27x0.c | 4 ++++
hw/misc/aspeed_scu.c | 38 ++++++++++++++++++++++++++++++++++--
5 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 9e28bd4d2e..6f7f7d2766 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -39,6 +39,10 @@ struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
+
+ MemoryRegion dram_remap_alias[3];
+ MemoryRegion *dram;
+ int ssp_cpuid;
};
#define AST2400_A0_SILICON_REV 0x02000303U
@@ -73,6 +77,7 @@ struct AspeedSCUClass {
uint32_t nr_regs;
bool clkin_25Mhz;
const MemoryRegionOps *ops;
+ void (*dram_remap)(AspeedSCUState *s);
};
#define ASPEED_SCU_PROT_KEY 0x1688A8A8
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 0502a137f3..b788e6ca2a 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -101,6 +101,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(1));
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
+ object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index cba59ae11a..cf1339e2c7 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -198,6 +198,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
+ /* SDRAM remap alias used by PSP to access SSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[1]);
+ memory_region_add_subregion(&s->sdram,
+ memory_region_size(&s->scu->dram_remap_alias[1]),
+ &s->scu->dram_remap_alias[0]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 74a004adca..ae8b22fc1c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -389,6 +389,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-strap1");
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key");
+ object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu),
+ "ssp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
@@ -740,6 +742,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
/* SCU */
+ object_property_set_link(OBJECT(&s->scu), "dram", OBJECT(s->dram_mr),
+ &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6829efa2dc..4b74e5adcb 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "qemu/units.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -602,12 +603,20 @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp)
TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
+
+ if (asc->dram_remap) {
+ if (!s->dram) {
+ error_setg(errp, TYPE_ASPEED_SCU ": 'dram' link not set");
+ return;
+ }
+ asc->dram_remap(s);
+ }
}
static const VMStateDescription vmstate_aspeed_scu = {
.name = "aspeed.scu",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
VMSTATE_END_OF_LIST()
@@ -619,6 +628,9 @@ static const Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
+ DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1),
+ DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
};
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
@@ -872,6 +884,27 @@ static const TypeInfo aspeed_2600_scu_info = {
.class_init = aspeed_2600_scu_class_init,
};
+static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
+{
+ if (s->ssp_cpuid > 0) {
+ /*
+ * The SSP coprocessor uses two memory aliases (remap1 and remap2)
+ * to access shared memory regions in the PSP DRAM:
+ *
+ * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM
+ * offset 0x2000000
+ * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM
+ * offset 0x0
+ */
+ memory_region_init_alias(&s->dram_remap_alias[0], OBJECT(s),
+ "ssp.dram.remap1", s->dram,
+ 0, 32 * MiB);
+ memory_region_init_alias(&s->dram_remap_alias[1], OBJECT(s),
+ "ssp.dram.remap2", s->dram,
+ 0x2c000000, 32 * MiB);
+ }
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -982,6 +1015,7 @@ static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
asc->clkin_25Mhz = true;
asc->ops = &aspeed_ast2700_scu_ops;
+ asc->dram_remap = aspeed_2700_scu_dram_remap_alias_init;
}
static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42e000000 (32MB) to TSP SDRAM offset 0x0
This region corresponds to the default SCU register value, which controls
the mapping between PSP and coprocessor memory windows.
Set TSP CPUID 5. SCU VMState version remains at 3, as it was already bumped in a
previous commit.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-tsp.c | 3 +++
hw/arm/aspeed_ast27x0.c | 2 ++
hw/misc/aspeed_scu.c | 15 +++++++++++++++
5 files changed, 23 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 6f7f7d2766..1e18dcd4a5 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -43,6 +43,7 @@ struct AspeedSCUState {
MemoryRegion dram_remap_alias[3];
MemoryRegion *dram;
int ssp_cpuid;
+ int tsp_cpuid;
};
#define AST2400_A0_SILICON_REV 0x02000303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index b788e6ca2a..e03f6870e7 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -103,6 +103,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(2));
object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
&error_abort);
+ object_property_set_int(OBJECT(&s->ca35), "tsp-cpuid", 5,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 46691080d1..5d2977b45c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -198,6 +198,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
+ /* SDRAM remap alias used by PSP to access TSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[2]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ae8b22fc1c..6e4b456b8c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -391,6 +391,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-prot-key");
object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu),
"ssp-cpuid");
+ object_property_add_alias(obj, "tsp-cpuid", OBJECT(&s->scu),
+ "tsp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4b74e5adcb..ec373147ab 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -629,6 +629,7 @@ static const Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1),
+ DEFINE_PROP_INT32("tsp-cpuid", AspeedSCUState, tsp_cpuid, -1),
DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION,
MemoryRegion *),
};
@@ -903,6 +904,20 @@ static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
"ssp.dram.remap2", s->dram,
0x2c000000, 32 * MiB);
}
+
+ if (s->tsp_cpuid > 0) {
+ /*
+ * The TSP coprocessor uses one memory alias (remap) to access a shared
+ * region in the PSP DRAM:
+ *
+ * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM
+ * offset 0x0
+ *
+ */
+ memory_region_init_alias(&s->dram_remap_alias[2], OBJECT(s),
+ "tsp.dram.remap", s->dram,
+ 0x2e000000, 32 * MiB);
+ }
}
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42e000000 (32MB) to TSP SDRAM offset 0x0
This region corresponds to the default SCU register value, which controls
the mapping between PSP and coprocessor memory windows.
Set TSP CPUID 5. SCU VMState version remains at 3, as it was already bumped in a
previous commit.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast27x0-fc.c | 2 ++
hw/arm/aspeed_ast27x0-tsp.c | 3 +++
hw/arm/aspeed_ast27x0.c | 2 ++
hw/misc/aspeed_scu.c | 15 +++++++++++++++
5 files changed, 23 insertions(+)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 6f7f7d2766..1e18dcd4a5 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -43,6 +43,7 @@ struct AspeedSCUState {
MemoryRegion dram_remap_alias[3];
MemoryRegion *dram;
int ssp_cpuid;
+ int tsp_cpuid;
};
#define AST2400_A0_SILICON_REV 0x02000303U
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index b788e6ca2a..e03f6870e7 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -103,6 +103,8 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(2));
object_property_set_int(OBJECT(&s->ca35), "ssp-cpuid", 4,
&error_abort);
+ object_property_set_int(OBJECT(&s->ca35), "tsp-cpuid", 5,
+ &error_abort);
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 46691080d1..5d2977b45c 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -198,6 +198,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
&s->scu_alias);
+ /* SDRAM remap alias used by PSP to access TSP SDRAM */
+ memory_region_add_subregion(&s->sdram, 0, &s->scu->dram_remap_alias[2]);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ae8b22fc1c..6e4b456b8c 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -391,6 +391,8 @@ static void aspeed_soc_ast2700_init(Object *obj)
"hw-prot-key");
object_property_add_alias(obj, "ssp-cpuid", OBJECT(&s->scu),
"ssp-cpuid");
+ object_property_add_alias(obj, "tsp-cpuid", OBJECT(&s->scu),
+ "tsp-cpuid");
object_initialize_child(obj, "scuio", &s->scuio, TYPE_ASPEED_2700_SCUIO);
qdev_prop_set_uint32(DEVICE(&s->scuio), "silicon-rev",
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 4b74e5adcb..ec373147ab 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -629,6 +629,7 @@ static const Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
DEFINE_PROP_INT32("ssp-cpuid", AspeedSCUState, ssp_cpuid, -1),
+ DEFINE_PROP_INT32("tsp-cpuid", AspeedSCUState, tsp_cpuid, -1),
DEFINE_PROP_LINK("dram", AspeedSCUState, dram, TYPE_MEMORY_REGION,
MemoryRegion *),
};
@@ -903,6 +904,20 @@ static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
"ssp.dram.remap2", s->dram,
0x2c000000, 32 * MiB);
}
+
+ if (s->tsp_cpuid > 0) {
+ /*
+ * The TSP coprocessor uses one memory alias (remap) to access a shared
+ * region in the PSP DRAM:
+ *
+ * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM
+ * offset 0x0
+ *
+ */
+ memory_region_init_alias(&s->dram_remap_alias[2], OBJECT(s),
+ "tsp.dram.remap", s->dram,
+ 0x2e000000, 32 * MiB);
+ }
}
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x200):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120):
- Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding SSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the SSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_CTRL_0 to release
the hold and power on SSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x204):
- The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_RST_CLR_1,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. SSP Power Control Logic:
- `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and invokes
`arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).
- `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.
6. Register Initialization and Definitions:
- Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (0x200),
and SYS_RST_CLR_1 (0x204).
- Updates the reset values for these registers during SCU initialization.
The default values are based on EVB (evaluation board) register dump observations.
This patch enables proper modeling of SSP lifecycle management across reset,
hold, and power-on states for the AST2700 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 107 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ec373147ab..506a4fa73f 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -21,6 +21,7 @@
#include "qemu/module.h"
#include "trace.h"
#include "qemu/units.h"
+#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -144,6 +145,17 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+/* SSP TSP */
+#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SSP_TSP_ENABLE BIT(0)
+#define AST2700_SSP_TSP_RST BIT(1)
+#define AST2700_SSP_TSP_RST_RB BIT(8)
+#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
+#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
+#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
+#define AST2700_SCU_SYS_RST_SSP BIT(30)
+
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
@@ -920,6 +932,35 @@ static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
}
}
+static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val &= ~AST2700_SSP_TSP_RST_SRC_RB;
+ if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {
+ val &= ~AST2700_SSP_TSP_RST_RB;
+ arm_set_cpu_on_and_reset(cpuid);
+ }
+
+ s->regs[reg] = val;
+}
+
+static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val |= AST2700_SSP_TSP_RST_RB;
+ val |= AST2700_SSP_TSP_RST_SRC_RB;
+ if (val & AST2700_SSP_TSP_RST) {
+ val |= AST2700_SSP_TSP_RST_HOLD_RB;
+ }
+ arm_set_cpu_off(cpuid);
+
+ s->regs[reg] = val;
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -951,6 +992,9 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
+ uint32_t active;
+ uint32_t oldval;
+ int cpuid;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -962,6 +1006,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_0:
+ cpuid = s->ssp_cpuid;
+ if (cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[reg];
+ data &= 0xff;
+ active = oldval ^ data;
+
+ /*
+ * If reset bit is being released (1 -> 0) and no other reset source
+ * is active, clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ if ((oldval & AST2700_SSP_TSP_RST_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+ }
+
+ /*
+ * If ENABLE bit is newly set and reset state is ready,
+ * clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_ENABLE) &&
+ (oldval & AST2700_SSP_TSP_RST_RB) &&
+ (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+
+ /* Auto-clear the ENABLE bit (one-shot behavior) */
+ data &= ~AST2700_SSP_TSP_ENABLE;
+ s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
+ return;
+ case AST2700_SCU_SYS_RST_CTRL_1:
+ if (s->ssp_cpuid < 0) {
+ return;
+ }
+ if (data & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_off(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_1:
+ if (s->ssp_cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_1];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_on(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -989,6 +1090,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1014,6 +1117,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[AST2700_SILICON_REV] = s->silicon_rev;
s->regs[AST2700_HW_STRAP1] = s->hw_strap1;
+
+ if (s->ssp_cpuid > 0) {
+ arm_set_cpu_off(s->ssp_cpuid);
+ }
}
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x200):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120):
- Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding SSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the SSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_CTRL_0 to release
the hold and power on SSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x204):
- The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_RST_CLR_1,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. SSP Power Control Logic:
- `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and invokes
`arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).
- `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.
6. Register Initialization and Definitions:
- Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (0x200),
and SYS_RST_CLR_1 (0x204).
- Updates the reset values for these registers during SCU initialization.
The default values are based on EVB (evaluation board) register dump observations.
This patch enables proper modeling of SSP lifecycle management across reset,
hold, and power-on states for the AST2700 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 107 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ec373147ab..506a4fa73f 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -21,6 +21,7 @@
#include "qemu/module.h"
#include "trace.h"
#include "qemu/units.h"
+#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -144,6 +145,17 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+/* SSP TSP */
+#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SSP_TSP_ENABLE BIT(0)
+#define AST2700_SSP_TSP_RST BIT(1)
+#define AST2700_SSP_TSP_RST_RB BIT(8)
+#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
+#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
+#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
+#define AST2700_SCU_SYS_RST_SSP BIT(30)
+
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
@@ -920,6 +932,35 @@ static void aspeed_2700_scu_dram_remap_alias_init(AspeedSCUState *s)
}
}
+static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val &= ~AST2700_SSP_TSP_RST_SRC_RB;
+ if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {
+ val &= ~AST2700_SSP_TSP_RST_RB;
+ arm_set_cpu_on_and_reset(cpuid);
+ }
+
+ s->regs[reg] = val;
+}
+
+static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid,
+ int reg)
+{
+ uint32_t val = s->regs[reg];
+
+ val |= AST2700_SSP_TSP_RST_RB;
+ val |= AST2700_SSP_TSP_RST_SRC_RB;
+ if (val & AST2700_SSP_TSP_RST) {
+ val |= AST2700_SSP_TSP_RST_HOLD_RB;
+ }
+ arm_set_cpu_off(cpuid);
+
+ s->regs[reg] = val;
+}
+
static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
unsigned size)
{
@@ -951,6 +992,9 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
+ uint32_t active;
+ uint32_t oldval;
+ int cpuid;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -962,6 +1006,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_0:
+ cpuid = s->ssp_cpuid;
+ if (cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[reg];
+ data &= 0xff;
+ active = oldval ^ data;
+
+ /*
+ * If reset bit is being released (1 -> 0) and no other reset source
+ * is active, clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ if ((oldval & AST2700_SSP_TSP_RST_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+ }
+
+ /*
+ * If ENABLE bit is newly set and reset state is ready,
+ * clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_ENABLE) &&
+ (oldval & AST2700_SSP_TSP_RST_RB) &&
+ (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ handle_2700_ssp_tsp_on(s, cpuid, reg);
+ }
+
+ /* Auto-clear the ENABLE bit (one-shot behavior) */
+ data &= ~AST2700_SSP_TSP_ENABLE;
+ s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
+ return;
+ case AST2700_SCU_SYS_RST_CTRL_1:
+ if (s->ssp_cpuid < 0) {
+ return;
+ }
+ if (data & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_off(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_1:
+ if (s->ssp_cpuid < 0) {
+ return;
+ }
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_1];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_2700_ssp_tsp_on(s, s->ssp_cpuid, AST2700_SCU_SSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -989,6 +1090,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1014,6 +1117,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
memcpy(s->regs, asc->resets, asc->nr_regs * 4);
s->regs[AST2700_SILICON_REV] = s->silicon_rev;
s->regs[AST2700_HW_STRAP1] = s->hw_strap1;
+
+ if (s->ssp_cpuid > 0) {
+ arm_set_cpu_off(s->ssp_cpuid);
+ }
}
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 07/11] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x220):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump observations.
TSP reset control shares the same helper functions and register bit layout as SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 506a4fa73f..6aebdd630f 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,7 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
#define AST2700_SSP_TSP_RST_RB BIT(8)
@@ -155,6 +156,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -1007,7 +1011,10 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = s->ssp_cpuid;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ?
+ s->ssp_cpuid : s->tsp_cpuid;
+
if (cpuid < 0) {
return;
}
@@ -1063,6 +1070,28 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ if (s->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_off(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ if (s->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_on(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1091,7 +1120,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1121,6 +1152,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->ssp_cpuid > 0) {
arm_set_cpu_off(s->ssp_cpuid);
}
+
+ if (s->tsp_cpuid > 0) {
+ arm_set_cpu_off(s->tsp_cpuid);
+ }
}
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 07/11] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x220):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump observations.
TSP reset control shares the same helper functions and register bit layout as SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 506a4fa73f..6aebdd630f 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,7 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
#define AST2700_SSP_TSP_RST_RB BIT(8)
@@ -155,6 +156,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -1007,7 +1011,10 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = s->ssp_cpuid;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ?
+ s->ssp_cpuid : s->tsp_cpuid;
+
if (cpuid < 0) {
return;
}
@@ -1063,6 +1070,28 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ if (s->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_off(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ if (s->tsp_cpuid < 0) {
+ return;
+ }
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_2700_ssp_tsp_on(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1091,7 +1120,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
@@ -1121,6 +1152,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->ssp_cpuid > 0) {
arm_set_cpu_off(s->ssp_cpuid);
}
+
+ if (s->tsp_cpuid > 0) {
+ arm_set_cpu_off(s->tsp_cpuid);
+ }
}
static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 32MB) to SSP SDRAM
offset 0x2000000
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x42c000000 (size: 32MB) to SSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | SSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |
| remap1 base |---| | | - SCU_150: target addr |
| size: 32MB (SCU_14C) | | | | remap2 |
|------------------------------------------| | | |----------------------------|
| | | | | |
| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 |
| remap2 base | | | - SCU_148: target addr |
| size: 32MB (SCU_154) | |---> | remap1 |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6aebdd630f..27591f53c4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,12 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)
+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
@@ -993,6 +999,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
+ MemoryRegion *mr = NULL;
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
@@ -1050,6 +1057,37 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= ~AST2700_SSP_TSP_ENABLE;
s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
return;
+ case AST2700_SCU_SSP_CTRL_1:
+ case AST2700_SCU_SSP_CTRL_2:
+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ break;
+ case AST2700_SCU_SSP_REMAP_ADDR_1:
+ case AST2700_SCU_SSP_REMAP_ADDR_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_address(mr, data);
+ break;
+ case AST2700_SCU_SSP_REMAP_SIZE_1:
+ case AST2700_SCU_SSP_REMAP_SIZE_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(mr, data);
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (s->ssp_cpuid < 0) {
return;
@@ -1120,6 +1158,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,
+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
@@ -1151,6 +1195,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->ssp_cpuid > 0) {
arm_set_cpu_off(s->ssp_cpuid);
+ memory_region_set_address(&s->dram_remap_alias[0], 32 * MiB);
+ memory_region_set_alias_offset(&s->dram_remap_alias[0], 0);
+ memory_region_set_size(&s->dram_remap_alias[0], 32 * MiB);
+ memory_region_set_address(&s->dram_remap_alias[1], 0);
+ memory_region_set_alias_offset(&s->dram_remap_alias[1], 0x2c000000);
+ memory_region_set_size(&s->dram_remap_alias[1], 32 * MiB);
}
if (s->tsp_cpuid > 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 32MB) to SSP SDRAM
offset 0x2000000
- coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x42c000000 (size: 32MB) to SSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | SSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |
| remap1 base |---| | | - SCU_150: target addr |
| size: 32MB (SCU_14C) | | | | remap2 |
|------------------------------------------| | | |----------------------------|
| | | | | |
| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 |
| remap2 base | | | - SCU_148: target addr |
| size: 32MB (SCU_154) | |---> | remap1 |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 6aebdd630f..27591f53c4 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -147,6 +147,12 @@
/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)
+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SSP_TSP_ENABLE BIT(0)
#define AST2700_SSP_TSP_RST BIT(1)
@@ -993,6 +999,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
AspeedSCUState *s = ASPEED_SCU(opaque);
+ MemoryRegion *mr = NULL;
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
@@ -1050,6 +1057,37 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= ~AST2700_SSP_TSP_ENABLE;
s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
return;
+ case AST2700_SCU_SSP_CTRL_1:
+ case AST2700_SCU_SSP_CTRL_2:
+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ break;
+ case AST2700_SCU_SSP_REMAP_ADDR_1:
+ case AST2700_SCU_SSP_REMAP_ADDR_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_address(mr, data);
+ break;
+ case AST2700_SCU_SSP_REMAP_SIZE_1:
+ case AST2700_SCU_SSP_REMAP_SIZE_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+ &s->dram_remap_alias[0] : &s->dram_remap_alias[1];
+ if (s->ssp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(mr, data);
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (s->ssp_cpuid < 0) {
return;
@@ -1120,6 +1158,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
[AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,
+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
@@ -1151,6 +1195,12 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->ssp_cpuid > 0) {
arm_set_cpu_off(s->ssp_cpuid);
+ memory_region_set_address(&s->dram_remap_alias[0], 32 * MiB);
+ memory_region_set_alias_offset(&s->dram_remap_alias[0], 0);
+ memory_region_set_size(&s->dram_remap_alias[0], 32 * MiB);
+ memory_region_set_address(&s->dram_remap_alias[1], 0);
+ memory_region_set_alias_offset(&s->dram_remap_alias[1], 0x2c000000);
+ memory_region_set_size(&s->dram_remap_alias[1], 32 * MiB);
}
if (s->tsp_cpuid > 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 09/11] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.
coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | TSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 |
| remap base |------> | - fixed target addr |
| size: 32MB (SCU_194) | | |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 27591f53c4..69d26df818 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -159,6 +159,8 @@
#define AST2700_SSP_TSP_RST_RB BIT(8)
#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
@@ -1088,6 +1090,23 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= 0x3fffffff;
memory_region_set_size(mr, data);
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ mr = &s->dram_remap_alias[2];
+ if (s->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ mr = &s->dram_remap_alias[2];
+ if (s->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(mr, data);
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (s->ssp_cpuid < 0) {
return;
@@ -1165,6 +1184,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
@@ -1205,6 +1226,8 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->tsp_cpuid > 0) {
arm_set_cpu_off(s->tsp_cpuid);
+ memory_region_set_alias_offset(&s->dram_remap_alias[2], 0x2e000000);
+ memory_region_set_size(&s->dram_remap_alias[2], 32 * MiB);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 09/11] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.
coprocessor_sdram_remap[2]: maps PSP DRAM offset 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | TSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 |
| remap base |------> | - fixed target addr |
| size: 32MB (SCU_194) | | |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 27591f53c4..69d26df818 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -159,6 +159,8 @@
#define AST2700_SSP_TSP_RST_RB BIT(8)
#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
@@ -1088,6 +1090,23 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= 0x3fffffff;
memory_region_set_size(mr, data);
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ mr = &s->dram_remap_alias[2];
+ if (s->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_set_alias_offset(mr,
+ ((uint64_t) data << 4) & 0x3ffffffff);
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ mr = &s->dram_remap_alias[2];
+ if (s->tsp_cpuid < 0 || mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(mr, data);
+ break;
case AST2700_SCU_SYS_RST_CTRL_1:
if (s->ssp_cpuid < 0) {
return;
@@ -1165,6 +1184,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
@@ -1205,6 +1226,8 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
if (s->tsp_cpuid > 0) {
arm_set_cpu_off(s->tsp_cpuid);
+ memory_region_set_alias_offset(&s->dram_remap_alias[2], 0x2e000000);
+ memory_region_set_size(&s->dram_remap_alias[2], 32 * MiB);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
SSP and TSP now boot in a powered-off state by default. Enabling them requires
the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. This
behavior aligns with real hardware.
Update the AST2700 FC functional test to reflect this behavior by enabling
SSP and TSP from the U-Boot shell before booting OpenBMC. The test now
programs the required SCU registers, saves the environment, and boots the
system so that SSP and TSP are powered on when the PSP starts.
For the vbootrom test case, these steps are not required because vbootrom
already performs the necessary initialization. Therefore, the U-Boot shell
configuration is only applied to the manual loader test flow.
Additionally, switch SSP and TSP loading from ELF-based CPU loaders to
binary images loaded into PSP DRAM at fixed addresses, and remove the use
of snapshot mode.
Changes include:
- Add enable_ssp_tsp() to configure SCU registers via U-Boot
- Remove snapshot option from QEMU command line
- Load SSP binary at DRAM address 0x42C000000
- Load TSP binary at DRAM address 0x42E000000
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 35 +++++++++++--------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 8dbc8f234f..e0fb4890be 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -23,12 +23,22 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
- '-net', 'nic', '-net', 'user', '-snapshot')
+ '-net', 'nic', '-net', 'user')
self.vm.launch()
+ def enable_ssp_tsp(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'setenv bootcmd "mw 12c02204 40000000; mw 12c02120 1;'
+ 'mw 12c02224 00000200; mw 12c02160 1; run bootspi"', '=>')
+ exec_command_and_wait_for_pattern(self, 'saveenv', 'OK')
+ exec_command(self, 'boot')
+
def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'U-Boot 2023.10')
+ self.enable_ssp_tsp();
wait_for_console_pattern(self, '## Loading kernel from FIT Image')
wait_for_console_pattern(self, 'Starting kernel ...')
@@ -36,17 +46,6 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- def load_ast2700fc_coprocessor(self, name):
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
-
ASSET_SDK_V908_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
@@ -121,6 +120,14 @@ def start_ast2700fc_test(self, name):
'addr': '0x430080000',
'file': self.scratch_file(name, 'optee',
'tee-raw.bin')
+ },
+ {
+ 'addr': '0x42C000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-ssp.bin')
+ },
+ {
+ 'addr': '0x42E000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-tsp.bin')
}
]
@@ -134,13 +141,11 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
def start_ast2700fc_test_vbootrom(self, name):
self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
SSP and TSP now boot in a powered-off state by default. Enabling them requires
the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. This
behavior aligns with real hardware.
Update the AST2700 FC functional test to reflect this behavior by enabling
SSP and TSP from the U-Boot shell before booting OpenBMC. The test now
programs the required SCU registers, saves the environment, and boots the
system so that SSP and TSP are powered on when the PSP starts.
For the vbootrom test case, these steps are not required because vbootrom
already performs the necessary initialization. Therefore, the U-Boot shell
configuration is only applied to the manual loader test flow.
Additionally, switch SSP and TSP loading from ELF-based CPU loaders to
binary images loaded into PSP DRAM at fixed addresses, and remove the use
of snapshot mode.
Changes include:
- Add enable_ssp_tsp() to configure SCU registers via U-Boot
- Remove snapshot option from QEMU command line
- Load SSP binary at DRAM address 0x42C000000
- Load TSP binary at DRAM address 0x42E000000
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 35 +++++++++++--------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 8dbc8f234f..e0fb4890be 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -9,7 +9,7 @@
import os
from qemu_test import QemuSystemTest, Asset
-from qemu_test import wait_for_console_pattern
+from qemu_test import wait_for_console_pattern, exec_command
from qemu_test import exec_command_and_wait_for_pattern
@@ -23,12 +23,22 @@ def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.add_args('-device', 'e1000e,netdev=net1,bus=pcie.2')
self.vm.add_args('-netdev', 'user,id=net1')
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
- '-net', 'nic', '-net', 'user', '-snapshot')
+ '-net', 'nic', '-net', 'user')
self.vm.launch()
+ def enable_ssp_tsp(self):
+ wait_for_console_pattern(self, 'Hit any key to stop autoboot')
+ exec_command_and_wait_for_pattern(self, '\012', '=>')
+ exec_command_and_wait_for_pattern(self,
+ 'setenv bootcmd "mw 12c02204 40000000; mw 12c02120 1;'
+ 'mw 12c02224 00000200; mw 12c02160 1; run bootspi"', '=>')
+ exec_command_and_wait_for_pattern(self, 'saveenv', 'OK')
+ exec_command(self, 'boot')
+
def verify_openbmc_boot_and_login(self, name):
wait_for_console_pattern(self, 'U-Boot 2023.10')
+ self.enable_ssp_tsp();
wait_for_console_pattern(self, '## Loading kernel from FIT Image')
wait_for_console_pattern(self, 'Starting kernel ...')
@@ -36,17 +46,6 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- def load_ast2700fc_coprocessor(self, name):
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
-
ASSET_SDK_V908_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
@@ -121,6 +120,14 @@ def start_ast2700fc_test(self, name):
'addr': '0x430080000',
'file': self.scratch_file(name, 'optee',
'tee-raw.bin')
+ },
+ {
+ 'addr': '0x42C000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-ssp.bin')
+ },
+ {
+ 'addr': '0x42E000000',
+ 'file': self.scratch_file(name, 'zephyr-aspeed-tsp.bin')
}
]
@@ -134,13 +141,11 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
def start_ast2700fc_test_vbootrom(self, name):
self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
- self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc
2026-01-20 9:29 ` Jamin Lin via qemu development
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
-1 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 4fa1739cb5..a1f4366f87 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -391,6 +391,14 @@ Booting the ast2700fc machine
AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+There are two methods to boot the ast2700fc machine.
+
+Manual boot using ``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via QEMU loader devices.
+By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
+PSP through writes to SCU registers.
Steps to boot the AST2700fc machine:
@@ -401,8 +409,8 @@ Steps to boot the AST2700fc machine:
* bl31.bin
* optee/tee-raw.bin
* image-bmc
- * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
- * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
+ * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
+ * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
2. Execute the following command to start ``ast2700fc`` machine:
@@ -416,17 +424,38 @@ Steps to boot the AST2700fc machine:
-device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
+ -device loader,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin,force-raw=on \
+ -device loader,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin,force-raw=on \
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
- -device loader,file=${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=4 \
- -device loader,file=${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=5 \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
+Boot using a virtual boot ROM (-bios):
+
+In this method, the virtual boot ROM (vbootrom) handles the full initialization sequence.
+It starts the PSP, which then enables the SSP and TSP by programming the appropriate SCU
+registers, following the hardware behavior.
+
+Execute the following command to start ``ast2700fc`` machine:
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -bios ast27x0_bootrom.bin \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+Serial Console Redirection:
+
After launching QEMU, serial devices will be automatically redirected.
Example output:
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [PATCH v1 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc
@ 2026-01-20 9:29 ` Jamin Lin via qemu development
0 siblings, 0 replies; 35+ messages in thread
From: Jamin Lin via qemu development @ 2026-01-20 9:29 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, kane_chen
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 4fa1739cb5..a1f4366f87 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -391,6 +391,14 @@ Booting the ast2700fc machine
AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+There are two methods to boot the ast2700fc machine.
+
+Manual boot using ``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via QEMU loader devices.
+By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
+PSP through writes to SCU registers.
Steps to boot the AST2700fc machine:
@@ -401,8 +409,8 @@ Steps to boot the AST2700fc machine:
* bl31.bin
* optee/tee-raw.bin
* image-bmc
- * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
- * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
+ * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
+ * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
2. Execute the following command to start ``ast2700fc`` machine:
@@ -416,17 +424,38 @@ Steps to boot the AST2700fc machine:
-device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
+ -device loader,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin,force-raw=on \
+ -device loader,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin,force-raw=on \
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
- -device loader,file=${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=4 \
- -device loader,file=${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=5 \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
+Boot using a virtual boot ROM (-bios):
+
+In this method, the virtual boot ROM (vbootrom) handles the full initialization sequence.
+It starts the PSP, which then enables the SSP and TSP by programming the appropriate SCU
+registers, following the hardware behavior.
+
+Execute the following command to start ``ast2700fc`` machine:
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -bios ast27x0_bootrom.bin \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+Serial Console Redirection:
+
After launching QEMU, serial devices will be automatically redirected.
Example output:
--
2.43.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-20 9:29 ` Jamin Lin via qemu development
(?)
@ 2026-01-26 9:01 ` Cédric Le Goater
2026-01-27 5:07 ` Jamin Lin
-1 siblings, 1 reply; 35+ messages in thread
From: Cédric Le Goater @ 2026-01-26 9:01 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, kane_chen
On 1/20/26 10:29, Jamin Lin via qemu development wrote:
> This commit adds two MemoryRegion aliases to support PSP access to
> SSP SDRAM through shared memory remapping, as defined by the default SCU
> configuration.
>
> The SSP exposes two DRAM aliases:
> - remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000
> - remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0
>
> These regions correspond to the default SCU register values, which control
> the mapping between PSP and coprocessor memory windows.
>
> Set SSP CPUID 4 and bumps the SCU VMState version to 3.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/misc/aspeed_scu.h | 5 +++++
> hw/arm/aspeed_ast27x0-fc.c | 2 ++
> hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
> hw/arm/aspeed_ast27x0.c | 4 ++++
> hw/misc/aspeed_scu.c | 38 ++++++++++++++++++++++++++++++++++--
> 5 files changed, 53 insertions(+), 2 deletions(-)
make check fails with :
Unexpected error in aspeed_scu_realize() at ../hw/misc/aspeed_scu.c:609:
qemu-system-aarch64: aspeed.scu: 'dram' link not set
Thanks,
C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-26 9:01 ` Cédric Le Goater
@ 2026-01-27 5:07 ` Jamin Lin
2026-01-27 6:09 ` Jamin Lin
0 siblings, 1 reply; 35+ messages in thread
From: Jamin Lin @ 2026-01-27 5:07 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
Hi Cédric
> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> On 1/20/26 10:29, Jamin Lin via qemu development wrote:
> > This commit adds two MemoryRegion aliases to support PSP access to SSP
> > SDRAM through shared memory remapping, as defined by the default SCU
> > configuration.
> >
> > The SSP exposes two DRAM aliases:
> > - remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset
> 0x2000000
> > - remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset
> > 0x0
> >
> > These regions correspond to the default SCU register values, which
> > control the mapping between PSP and coprocessor memory windows.
> >
> > Set SSP CPUID 4 and bumps the SCU VMState version to 3.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/misc/aspeed_scu.h | 5 +++++
> > hw/arm/aspeed_ast27x0-fc.c | 2 ++
> > hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
> > hw/arm/aspeed_ast27x0.c | 4 ++++
> > hw/misc/aspeed_scu.c | 38
> ++++++++++++++++++++++++++++++++++--
> > 5 files changed, 53 insertions(+), 2 deletions(-)
> make check fails with :
>
> Unexpected error in aspeed_scu_realize() at ../hw/misc/aspeed_scu.c:609:
> qemu-system-aarch64: aspeed.scu: 'dram' link not set
>
Sorry, I cannot reproduce the issue on my side. My qemu version:
https://github.com/qemu/qemu/commit/fea2d7a784fc3627a8aa72875f51fe7634b04b81
I tested on Ubuntu 24.04 and obtained the following results:
Ok: 379
Fail: 0
Skipped: 14
Full log written to /home/jamin_lin/qemu-work/debug-ssp-review/build/meson-logs/testlog.txt
I also tested on Ubuntu 22.04 and got the same test results.
(qemu) jamin@aspeed-fw01:~/qemu-work/build$ make check
[1/48] Generating qemu-version.h with a custom command (wrapped by meson to capture output)
[2/34] Generating tests/include/QAPI test (include) with a custom command
/home/jamin/qemu-work/build/pyvenv/bin/meson test --no-rebuild -t 1 --num-processes 1 --print-errorlogs --suite block --suite decodetree --suite func --suite func-aarch64 --suite func-arm --suite func-quick --suite qapi-frontend --suite qapi-interop --suite qapi-schema --suite qga --suite qtest --suite qtest-aarch64 --suite qtest-arm --suite slirp --suite softfloat --suite softfloat-compare --suite softfloat-conv --suite softfloat-ops --suite tracetool --suite unit
1/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bios-tables-test OK 92.91s 14 subtests passed
2/390 qtest+qtest-arm - qemu:qtest-arm/qom-test OK 110.65s 83 subtests passed
3/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qom-test OK 132.70s 93 subtests passed
4/390 qtest+qtest-arm - qemu:qtest-arm/device-introspect-test OK 12.61s 6 subtests passed
5/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/device-introspect-test OK 12.97s 6 subtests passed
6/390 qtest+qtest-arm - qemu:qtest-arm/cdrom-test SKIP 0.02s
7/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/cdrom-test SKIP 0.02s
8/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_usart-test OK 1.26s 7 subtests passed
9/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/migration-test OK 14.45s 8 subtests passed
10/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_smc-test OK 85.36s 34 subtests passed
11/390 qtest+qtest-arm - qemu:qtest-arm/boot-serial-test OK 0.89s 3 subtests passed
12/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/boot-serial-test OK 0.53s 1 subtests passed
13/390 unit - qemu:test-crypto-block SKIP 0.02s
14/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_pwm-test OK 11.35s 3 subtests passed
15/390 qtest+qtest-arm - qemu:qtest-arm/test-hmp OK 89.69s 84 subtests passed
16/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/test-hmp OK 102.52s 94 subtests passed
17/390 unit - qemu:test-aio-multithread OK 7.44s 6 subtests passed
18/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_watchdog_timer-test OK 6.56s 15 subtests passed
19/390 qtest+qtest-arm - qemu:qtest-arm/qmp-cmd-test OK 10.29s 64 subtests passed
20/390 qtest+qtest-arm - qemu:qtest-arm/qos-test OK 23.63s 97 subtests passed
21/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qmp-cmd-test OK 10.40s 64 subtests passed
22/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qos-test OK 33.04s 128 subtests passed
23/390 func-quick+func-arm - qemu:func-arm-migration OK 1.24s 2 subtests passed
24/390 func-quick+func-arm - qemu:func-arm-empty_cpu_model OK 0.23s 1 subtests passed
25/390 func-quick+func-arm - qemu:func-arm-info_usernet OK 0.29s 1 subtests passed
26/390 func-quick+func-arm - qemu:func-arm-linters SKIP 0.13s 0 subtests passed
27/390 func-quick+func-arm - qemu:func-arm-version OK 0.21s 1 subtests passed
28/390 func-quick+func-arm - qemu:func-arm-vnc SKIP 0.41s 0 subtests passed
29/390 func-quick+func-aarch64 - qemu:func-aarch64-migration OK 1.22s 2 subtests passed
30/390 func-quick+func-aarch64 - qemu:func-aarch64-vmstate SKIP 0.15s 0 subtests passed
31/390 func-quick+func-aarch64 - qemu:func-aarch64-empty_cpu_model OK 0.21s 1 subtests passed
32/390 func-quick+func-aarch64 - qemu:func-aarch64-info_usernet OK 0.28s 1 subtests passed
33/390 func-quick+func-aarch64 - qemu:func-aarch64-linters SKIP 0.13s 0 subtests passed
34/390 func-quick+func-aarch64 - qemu:func-aarch64-version OK 0.23s 1 subtests passed
35/390 func-quick+func-aarch64 - qemu:func-aarch64-vnc SKIP 0.42s 0 subtests passed
36/390 unit - qemu:test-replication OK 4.45s 13 subtests passed
37/390 unit - qemu:test-bufferiszero OK 1.10s 1 subtests passed
38/390 qtest+qtest-arm - qemu:qtest-arm/sse-timer-test OK 0.32s 3 subtests passed
39/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-dualtimer-test OK 0.17s 2 subtests passed
40/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-timer-test OK 0.18s 1 subtests passed
41/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-watchdog-test OK 1.29s 7 subtests passed
42/390 qtest+qtest-arm - qemu:qtest-arm/pflash-cfi02-test OK 1.70s 4 subtests passed
43/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_gpio-test OK 0.48s 2 subtests passed
44/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_hace-test OK 9.99s 30 subtests passed
45/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_scu-test OK 1.29s 4 subtests passed
46/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_adc-test OK 2.89s 6 subtests passed
47/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_gpio-test OK 0.25s 18 subtests passed
48/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_rng-test OK 0.24s 2 subtests passed
49/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_sdhci-test OK 0.99s 3 subtests passed
50/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_smbus-test OK 8.79s 40 subtests passed
51/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_timer-test OK 0.35s 180 subtests passed
52/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_emc-test OK 1.34s 6 subtests passed
53/390 qtest+qtest-arm - qemu:qtest-arm/hexloader-test OK 0.18s 1 subtests passed
54/390 qtest+qtest-arm - qemu:qtest-arm/tpm-tis-i2c-test OK 0.75s 6 subtests passed
55/390 qtest+qtest-arm - qemu:qtest-arm/test-arm-mptimer OK 0.22s 61 subtests passed
56/390 qtest+qtest-arm - qemu:qtest-arm/microbit-test OK 4.17s 6 subtests passed
57/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_exti-test OK 0.20s 9 subtests passed
58/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_syscfg-test OK 0.20s 10 subtests passed
59/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_rcc-test OK 0.19s 5 subtests passed
60/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_gpio-test OK 0.28s 14 subtests passed
61/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_fsi-test OK 0.42s 4 subtests passed
62/390 qtest+qtest-arm - qemu:qtest-arm/dm163-test OK 0.58s 3 subtests passed
63/390 qtest+qtest-arm - qemu:qtest-arm/arm-cpu-features OK 0.55s 1 subtests passed
64/390 qtest+qtest-arm - qemu:qtest-arm/machine-none-test OK 0.16s 1 subtests passed
65/390 qtest+qtest-arm - qemu:qtest-arm/qmp-test OK 0.65s 4 subtests passed
66/390 qtest+qtest-arm - qemu:qtest-arm/readconfig-test OK 0.16s 1 subtests passed
67/390 qtest+qtest-arm - qemu:qtest-arm/netdev-socket OK 3.70s 10 subtests passed
68/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-device-test OK 0.22s 5 subtests passed
69/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-device-swtpm-test SKIP 0.02s 0 subtests passed
70/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/xlnx-canfd-test OK 2.48s 3 subtests passed
71/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/xlnx-versal-trng-test OK 0.85s 5 subtests passed
72/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bcm2835-dma-test OK 0.19s 1 subtests passed
73/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bcm2835-i2c-test OK 0.19s 3 subtests passed
74/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-i2c-test OK 0.76s 6 subtests passed
75/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-gpio-test OK 1.27s 2 subtests passed
76/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-hace-test OK 6.53s 11 subtests passed
77/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-sgpio-test OK 11.10s 3 subtests passed
78/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-smc-test OK 2.39s 8 subtests passed
79/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/npcm_gmac-test OK 1.00s 4 subtests passed
80/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/iommu-smmuv3-test OK 0.77s 3 subtests passed
81/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/cxl-test OK 0.28s 1 subtests passed
82/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/arm-cpu-features OK 1.19s 3 subtests passed
83/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/numa-test OK 1.16s 5 subtests passed
84/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/machine-none-test OK 0.16s 1 subtests passed
85/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qmp-test OK 0.66s 4 subtests passed
86/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/readconfig-test OK 0.16s 1 subtests passed
87/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/netdev-socket OK 3.71s 10 subtests passed
88/390 unit - qemu:check-block-qdict OK 0.02s 10 subtests passed
89/390 unit - qemu:check-qdict OK 0.02s 15 subtests passed
90/390 unit - qemu:check-qnum OK 0.01s 8 subtests passed
91/390 unit - qemu:check-qstring OK 0.01s 4 subtests passed
92/390 unit - qemu:check-qlist OK 0.01s 4 subtests passed
93/390 unit - qemu:check-qnull OK 0.01s 2 subtests passed
94/390 unit - qemu:check-qobject OK 0.01s 7 subtests passed
95/390 unit - qemu:check-qjson OK 0.42s 31 subtests passed
96/390 unit - qemu:check-qlit OK 0.01s 2 subtests passed
97/390 unit - qemu:test-error-report OK 0.04s 5 subtests passed
98/390 unit - qemu:test-qobject-output-visitor OK 0.02s 16 subtests passed
99/390 unit - qemu:test-clone-visitor OK 0.02s 7 subtests passed
100/390 unit - qemu:test-qobject-input-visitor OK 0.02s 42 subtests passed
101/390 unit - qemu:test-forward-visitor OK 0.02s 7 subtests passed
102/390 unit - qemu:test-string-input-visitor OK 0.04s 8 subtests passed
103/390 unit - qemu:test-string-output-visitor OK 0.02s 14 subtests passed
104/390 unit - qemu:test-visitor-serialization OK 0.03s 156 subtests passed
105/390 unit - qemu:test-bitmap OK 0.01s 2 subtests passed
106/390 unit - qemu:test-resv-mem OK 0.01s 3 subtests passed
107/390 unit - qemu:test-x86-topo OK 0.01s 1 subtests passed
108/390 unit - qemu:test-cutils OK 0.02s 179 subtests passed
109/390 unit - qemu:test-div128 OK 0.01s 2 subtests passed
110/390 unit - qemu:test-shift128 OK 0.02s 2 subtests passed
111/390 unit - qemu:test-mul64 OK 0.02s 2 subtests passed
112/390 unit - qemu:test-int128 OK 0.02s 11 subtests passed
113/390 unit - qemu:rcutorture OK 2.03s 2 subtests passed
114/390 unit - qemu:test-rcu-list OK 4.03s 3 subtests passed
115/390 unit - qemu:test-rcu-simpleq OK 4.03s 3 subtests passed
116/390 unit - qemu:test-rcu-tailq OK 4.03s 3 subtests passed
117/390 unit - qemu:test-rcu-slist OK 4.04s 3 subtests passed
118/390 unit - qemu:test-qdist OK 0.02s 8 subtests passed
119/390 unit - qemu:test-qht OK 0.64s 2 subtests passed
120/390 unit - qemu:test-qtree OK 0.02s 4 subtests passed
121/390 unit - qemu:test-bitops OK 0.02s 6 subtests passed
122/390 unit - qemu:test-bitcnt OK 0.02s 4 subtests passed
123/390 unit - qemu:test-qgraph OK 0.02s 23 subtests passed
124/390 unit - qemu:check-qom-interface OK 0.02s 2 subtests passed
125/390 unit - qemu:check-qom-proplist OK 0.02s 9 subtests passed
126/390 unit - qemu:test-qemu-opts OK 0.02s 19 subtests passed
127/390 unit - qemu:test-keyval OK 0.02s 13 subtests passed
128/390 unit - qemu:test-logging OK 0.03s 4 subtests passed
129/390 unit - qemu:test-qapi-util OK 0.02s 2 subtests passed
130/390 unit - qemu:test-interval-tree OK 0.01s 6 subtests passed
131/390 unit - qemu:test-fifo OK 0.01s 10 subtests passed
132/390 unit - qemu:test-qmp-event OK 0.02s 6 subtests passed
133/390 unit - qemu:test-coroutine OK 0.02s 12 subtests passed
134/390 unit - qemu:test-aio OK 3.53s 27 subtests passed
135/390 unit - qemu:test-throttle OK 0.02s 17 subtests passed
136/390 unit - qemu:test-thread-pool OK 4.04s 6 subtests passed
137/390 unit - qemu:test-hbitmap OK 0.24s 40 subtests passed
138/390 unit - qemu:test-bdrv-drain OK 0.12s 30 subtests passed
139/390 unit - qemu:test-bdrv-graph-mod OK 0.02s 5 subtests passed
140/390 unit - qemu:test-blockjob OK 0.02s 8 subtests passed
141/390 unit - qemu:test-blockjob-txn OK 0.02s 7 subtests passed
142/390 unit - qemu:test-block-backend OK 0.01s 2 subtests passed
143/390 unit - qemu:test-block-iothread OK 0.04s 22 subtests passed
144/390 unit - qemu:test-write-threshold OK 0.02s 2 subtests passed
145/390 unit - qemu:test-crypto-hash OK 0.02s 6 subtests passed
146/390 unit - qemu:test-crypto-hmac OK 0.02s 4 subtests passed
147/390 unit - qemu:test-crypto-cipher SKIP 0.02s
148/390 unit - qemu:test-crypto-akcipher OK 0.02s 16 subtests passed
149/390 unit - qemu:test-crypto-secret OK 0.01s 10 subtests passed
150/390 unit - qemu:test-crypto-der OK 0.01s 4 subtests passed
151/390 unit - qemu:test-authz-simple OK 0.02s 1 subtests passed
152/390 unit - qemu:test-authz-list OK 0.02s 6 subtests passed
153/390 unit - qemu:test-authz-listfile OK 0.02s 5 subtests passed
154/390 unit - qemu:test-io-task OK 0.02s 5 subtests passed
155/390 unit - qemu:test-io-channel-socket OK 0.10s 9 subtests passed
156/390 unit - qemu:test-io-channel-file OK 0.04s 5 subtests passed
157/390 unit - qemu:test-io-channel-command OK 0.21s 4 subtests passed
158/390 unit - qemu:test-io-channel-buffer OK 0.03s 1 subtests passed
159/390 unit - qemu:test-io-channel-null OK 0.02s 1 subtests passed
160/390 unit - qemu:test-crypto-ivgen OK 0.02s 9 subtests passed
161/390 unit - qemu:test-crypto-afsplit OK 0.05s 4 subtests passed
162/390 unit - qemu:test-timed-average OK 0.02s 1 subtests passed
163/390 unit - qemu:test-uuid OK 0.02s 6 subtests passed
164/390 unit - qemu:test-image-locking OK 0.02s 2 subtests passed
165/390 unit - qemu:test-nested-aio-poll OK 0.01s 1 subtests passed
166/390 unit - qemu:test-crypto-pbkdf SKIP 0.02s
167/390 unit - qemu:ptimer-test OK 0.04s 576 subtests passed
168/390 unit - qemu:test-iov OK 0.59s 6 subtests passed
169/390 unit - qemu:test-opts-visitor OK 0.05s 33 subtests passed
170/390 unit - qemu:test-xs-node OK 0.01s 7 subtests passed
171/390 unit - qemu:test-virtio-dmabuf OK 0.01s 5 subtests passed
172/390 unit - qemu:test-qmp-cmds OK 0.01s 10 subtests passed
173/390 unit - qemu:test-xbzrle OK 0.04s 6 subtests passed
174/390 unit - qemu:test-util-sockets OK 0.01s 21 subtests passed
175/390 unit - qemu:test-base64 OK 0.02s 4 subtests passed
176/390 unit - qemu:test-smp-parse OK 0.03s 10 subtests passed
177/390 unit - qemu:test-vmstate OK 0.02s 23 subtests passed
178/390 unit - qemu:test-yank OK 0.02s 6 subtests passed
179/390 unit - qemu:test-util-filemonitor OK 0.06s 1 subtests passed
180/390 unit - qemu:test-char OK 2.13s 40 subtests passed
181/390 unit - qemu:test-qdev-global-props OK 0.04s 4 subtests passed
182/390 unit - qemu:test-qga OK 4.18s 29 subtests passed
183/390 slirp:ping OK 0.12s
184/390 slirp:ncsi OK 0.02s
185/390 unit+qga - qemu:qga-ssh-test OK 0.03s
186/390 unit - qemu:xml-preprocess OK 0.23s
187/390 qapi-schema+qapi-interop - qemu:QAPI firmware.json regression test OK 0.09s
188/390 qapi-schema+qapi-interop - qemu:QAPI vhost-user.json regression test OK 0.09s
189/390 block - qemu:io-qcow2-001 OK 1.23s 1 subtests passed
190/390 block - qemu:io-qcow2-002 OK 1.48s 1 subtests passed
191/390 block - qemu:io-qcow2-003 OK 1.24s 1 subtests passed
192/390 block - qemu:io-qcow2-004 OK 0.49s 1 subtests passed
193/390 block - qemu:io-qcow2-005 OK 0.47s 1 subtests passed
194/390 block - qemu:io-qcow2-007 OK 1.46s 1 subtests passed
195/390 block - qemu:io-qcow2-008 OK 1.21s 1 subtests passed
196/390 block - qemu:io-qcow2-009 OK 0.38s 1 subtests passed
197/390 block - qemu:io-qcow2-010 OK 0.39s 1 subtests passed
198/390 block - qemu:io-qcow2-011 OK 0.68s 1 subtests passed
199/390 block - qemu:io-qcow2-012 OK 0.34s 1 subtests passed
200/390 block - qemu:io-qcow2-013 OK 7.30s 1 subtests passed
201/390 block - qemu:io-qcow2-017 OK 0.99s 1 subtests passed
202/390 block - qemu:io-qcow2-018 OK 0.97s 1 subtests passed
203/390 block - qemu:io-qcow2-019 OK 1.52s 1 subtests passed
204/390 block - qemu:io-qcow2-020 OK 1.98s 1 subtests passed
205/390 block - qemu:io-qcow2-021 OK 0.86s 1 subtests passed
206/390 block - qemu:io-qcow2-022 OK 1.76s 1 subtests passed
207/390 block - qemu:io-qcow2-024 OK 3.59s 1 subtests passed
208/390 block - qemu:io-qcow2-025 OK 1.78s 1 subtests passed
209/390 block - qemu:io-qcow2-027 OK 0.42s 1 subtests passed
210/390 block - qemu:io-qcow2-029 OK 1.02s 1 subtests passed
211/390 block - qemu:io-qcow2-031 OK 0.95s 1 subtests passed
212/390 block - qemu:io-qcow2-032 OK 0.43s 1 subtests passed
213/390 block - qemu:io-qcow2-033 OK 1.78s 1 subtests passed
214/390 block - qemu:io-qcow2-034 OK 1.66s 1 subtests passed
215/390 block - qemu:io-qcow2-035 OK 0.69s 1 subtests passed
216/390 block - qemu:io-qcow2-036 OK 1.72s 1 subtests passed
217/390 block - qemu:io-qcow2-037 OK 1.52s 1 subtests passed
218/390 block - qemu:io-qcow2-038 OK 0.96s 1 subtests passed
219/390 block - qemu:io-qcow2-039 OK 1.93s 1 subtests passed
220/390 block - qemu:io-qcow2-040 OK 11.63s 1 subtests passed
221/390 block - qemu:io-qcow2-041 OK 20.36s 1 subtests passed
222/390 block - qemu:io-qcow2-042 OK 0.48s 1 subtests passed
223/390 block - qemu:io-qcow2-043 OK 1.40s 1 subtests passed
224/390 block - qemu:io-qcow2-046 OK 0.57s 1 subtests passed
225/390 block - qemu:io-qcow2-047 OK 0.36s 1 subtests passed
226/390 block - qemu:io-qcow2-048 OK 0.73s 1 subtests passed
227/390 block - qemu:io-qcow2-049 SKIP 0.25s 0 subtests passed
228/390 block - qemu:io-qcow2-050 OK 0.65s 1 subtests passed
229/390 block - qemu:io-qcow2-052 OK 1.15s 1 subtests passed
230/390 block - qemu:io-qcow2-053 OK 0.42s 1 subtests passed
231/390 block - qemu:io-qcow2-054 OK 0.48s 1 subtests passed
232/390 block - qemu:io-qcow2-060 OK 5.65s 1 subtests passed
233/390 block - qemu:io-qcow2-061 OK 6.55s 1 subtests passed
234/390 block - qemu:io-qcow2-062 OK 0.40s 1 subtests passed
235/390 block - qemu:io-qcow2-063 OK 1.08s 1 subtests passed
236/390 block - qemu:io-qcow2-066 OK 1.35s 1 subtests passed
237/390 block - qemu:io-qcow2-069 OK 0.45s 1 subtests passed
238/390 block - qemu:io-qcow2-071 OK 1.25s 1 subtests passed
239/390 block - qemu:io-qcow2-072 OK 0.42s 1 subtests passed
240/390 block - qemu:io-qcow2-073 OK 1.83s 1 subtests passed
241/390 block - qemu:io-qcow2-074 OK 0.65s 1 subtests passed
242/390 block - qemu:io-qcow2-079 OK 1.56s 1 subtests passed
243/390 block - qemu:io-qcow2-080 OK 12.02s 1 subtests passed
244/390 block - qemu:io-qcow2-086 OK 0.46s 1 subtests passed
245/390 block - qemu:io-qcow2-089 OK 0.82s 1 subtests passed
246/390 block - qemu:io-qcow2-090 OK 0.38s 1 subtests passed
247/390 block - qemu:io-qcow2-097 OK 2.60s 1 subtests passed
248/390 block - qemu:io-qcow2-098 OK 1.39s 1 subtests passed
249/390 block - qemu:io-qcow2-099 OK 0.97s 1 subtests passed
250/390 block - qemu:io-qcow2-103 OK 0.70s 1 subtests passed
251/390 block - qemu:io-qcow2-104 OK 0.50s 1 subtests passed
252/390 block - qemu:io-qcow2-105 OK 0.60s 1 subtests passed
253/390 block - qemu:io-qcow2-107 OK 0.36s 1 subtests passed
254/390 block - qemu:io-qcow2-108 SKIP 0.29s 0 subtests passed
255/390 block - qemu:io-qcow2-110 OK 0.66s 1 subtests passed
256/390 block - qemu:io-qcow2-111 OK 0.29s 1 subtests passed
257/390 block - qemu:io-qcow2-114 OK 0.81s 1 subtests passed
258/390 block - qemu:io-qcow2-117 OK 0.78s 1 subtests passed
259/390 block - qemu:io-qcow2-120 OK 0.50s 1 subtests passed
260/390 block - qemu:io-qcow2-126 OK 0.86s 1 subtests passed
261/390 block - qemu:io-qcow2-127 OK 1.25s 1 subtests passed
262/390 block - qemu:io-qcow2-133 OK 0.70s 1 subtests passed
263/390 block - qemu:io-qcow2-134 SKIP 0.25s 0 subtests passed
264/390 block - qemu:io-qcow2-137 OK 1.35s 1 subtests passed
265/390 block - qemu:io-qcow2-138 OK 0.59s 1 subtests passed
266/390 block - qemu:io-qcow2-140 OK 0.78s 1 subtests passed
267/390 block - qemu:io-qcow2-141 OK 0.72s 1 subtests passed
268/390 block - qemu:io-qcow2-143 OK 0.50s 1 subtests passed
269/390 block - qemu:io-qcow2-150 OK 0.32s 1 subtests passed
270/390 block - qemu:io-qcow2-154 OK 7.65s 1 subtests passed
271/390 block - qemu:io-qcow2-156 OK 2.00s 1 subtests passed
272/390 block - qemu:io-qcow2-158 SKIP 0.24s 0 subtests passed
273/390 block - qemu:io-qcow2-159 OK 16.99s 1 subtests passed
274/390 block - qemu:io-qcow2-161 OK 2.87s 1 subtests passed
275/390 block - qemu:io-qcow2-170 OK 0.55s 1 subtests passed
276/390 block - qemu:io-qcow2-172 SKIP 0.25s 0 subtests passed
277/390 block - qemu:io-qcow2-174 OK 0.35s 1 subtests passed
278/390 block - qemu:io-qcow2-176 OK 5.97s 1 subtests passed
279/390 block - qemu:io-qcow2-177 OK 1.94s 1 subtests passed
280/390 block - qemu:io-qcow2-179 OK 1.28s 1 subtests passed
281/390 block - qemu:io-qcow2-181 SKIP 0.74s 0 subtests passed
282/390 block - qemu:io-qcow2-184 OK 0.71s 1 subtests passed
283/390 block - qemu:io-qcow2-186 SKIP 0.33s 0 subtests passed
284/390 block - qemu:io-qcow2-187 OK 0.47s 1 subtests passed
285/390 block - qemu:io-qcow2-190 OK 4.16s 1 subtests passed
286/390 block - qemu:io-qcow2-191 OK 38.33s 1 subtests passed
287/390 block - qemu:io-qcow2-192 SKIP 0.23s 0 subtests passed
288/390 block - qemu:io-qcow2-195 OK 0.82s 1 subtests passed
289/390 block - qemu:io-qcow2-203 OK 0.52s 1 subtests passed
290/390 block - qemu:io-qcow2-214 OK 1.57s 1 subtests passed
291/390 block - qemu:io-qcow2-217 OK 0.48s 1 subtests passed
292/390 block - qemu:io-qcow2-220 SKIP 0.25s 0 subtests passed
293/390 block - qemu:io-qcow2-226 OK 0.37s 1 subtests passed
294/390 block - qemu:io-qcow2-229 OK 0.95s 1 subtests passed
295/390 block - qemu:io-qcow2-244 OK 3.16s 1 subtests passed
296/390 block - qemu:io-qcow2-249 OK 1.16s 1 subtests passed
297/390 block - qemu:io-qcow2-251 OK 1.64s 1 subtests passed
298/390 block - qemu:io-qcow2-252 OK 0.61s 1 subtests passed
299/390 block - qemu:io-qcow2-256 OK 0.66s 1 subtests passed
300/390 block - qemu:io-qcow2-265 OK 0.45s 1 subtests passed
301/390 block - qemu:io-qcow2-267 OK 3.34s 1 subtests passed
302/390 block - qemu:io-qcow2-268 OK 0.35s 1 subtests passed
303/390 block - qemu:io-qcow2-271 OK 26.94s 1 subtests passed
304/390 block - qemu:io-qcow2-283 OK 1.23s 1 subtests passed
305/390 block - qemu:io-qcow2-287 SKIP 0.41s 0 subtests passed
306/390 block - qemu:io-qcow2-290 OK 1.08s 1 subtests passed
307/390 block - qemu:io-qcow2-292 OK 0.56s 1 subtests passed
308/390 block - qemu:io-qcow2-299 OK 0.46s 1 subtests passed
309/390 block - qemu:io-qcow2-313 OK 0.60s 1 subtests passed
310/390 block - qemu:io-qcow2-314 OK 4.91s 1 subtests passed
311/390 block - qemu:io-qcow2-copy-before-write OK 4.50s 1 subtests passed
312/390 block - qemu:io-qcow2-detect-zeroes-registered-buf OK 0.35s 1 subtests passed
313/390 block - qemu:io-qcow2-iothreads-commit-active OK 0.68s 1 subtests passed
314/390 block - qemu:io-qcow2-iothreads-resize OK 0.47s 1 subtests passed
315/390 block - qemu:io-qcow2-iothreads-stream OK 0.77s 1 subtests passed
316/390 block - qemu:io-qcow2-mirror-sparse OK 6.94s 1 subtests passed
317/390 block - qemu:io-qcow2-nbd-multiconn SKIP 0.27s 0 subtests passed
318/390 block - qemu:io-qcow2-nbd-qemu-allocation OK 0.56s 1 subtests passed
319/390 block - qemu:io-qcow2-qemu-img-close-errors OK 2.00s 1 subtests passed
320/390 block - qemu:io-qcow2-qsd-jobs OK 0.47s 1 subtests passed
321/390 block - qemu:io-qcow2-regression-vhdx-log OK 0.41s 1 subtests passed
322/390 decodetree - qemu:err_argset1 OK 0.05s
323/390 decodetree - qemu:err_argset2 OK 0.05s
324/390 decodetree - qemu:err_field1 OK 0.05s
325/390 decodetree - qemu:err_field2 OK 0.04s
326/390 decodetree - qemu:err_field3 OK 0.04s
327/390 decodetree - qemu:err_field4 OK 0.06s
328/390 decodetree - qemu:err_field5 OK 0.06s
329/390 decodetree - qemu:err_field6 OK 0.05s
330/390 decodetree - qemu:err_field7 OK 0.05s
331/390 decodetree - qemu:err_field8 OK 0.05s
332/390 decodetree - qemu:err_field9 OK 0.05s
333/390 decodetree - qemu:err_field10 OK 0.04s
334/390 decodetree - qemu:err_init1 OK 0.04s
335/390 decodetree - qemu:err_init2 OK 0.05s
336/390 decodetree - qemu:err_init3 OK 0.05s
337/390 decodetree - qemu:err_init4 OK 0.05s
338/390 decodetree - qemu:err_overlap1 OK 0.06s
339/390 decodetree - qemu:err_overlap2 OK 0.06s
340/390 decodetree - qemu:err_overlap3 OK 0.06s
341/390 decodetree - qemu:err_overlap4 OK 0.05s
342/390 decodetree - qemu:err_overlap5 OK 0.05s
343/390 decodetree - qemu:err_overlap6 OK 0.06s
344/390 decodetree - qemu:err_overlap7 OK 0.06s
345/390 decodetree - qemu:err_overlap8 OK 0.04s
346/390 decodetree - qemu:err_overlap9 OK 0.06s
347/390 decodetree - qemu:err_pattern_group_empty OK 0.06s
348/390 decodetree - qemu:err_pattern_group_ident1 OK 0.05s
349/390 decodetree - qemu:err_pattern_group_ident2 OK 0.05s
350/390 decodetree - qemu:err_pattern_group_nest1 OK 0.06s
351/390 decodetree - qemu:err_pattern_group_nest2 OK 0.06s
352/390 decodetree - qemu:err_pattern_group_nest3 OK 0.05s
353/390 decodetree - qemu:err_pattern_group_overlap1 OK 0.05s
354/390 decodetree - qemu:err_width1 OK 0.04s
355/390 decodetree - qemu:err_width2 OK 0.04s
356/390 decodetree - qemu:err_width3 OK 0.05s
357/390 decodetree - qemu:err_width4 OK 0.05s
358/390 decodetree - qemu:succ_argset_type1 OK 0.05s
359/390 decodetree - qemu:succ_function OK 0.05s
360/390 decodetree - qemu:succ_ident1 OK 0.05s
361/390 decodetree - qemu:succ_infer1 OK 0.05s
362/390 decodetree - qemu:succ_named_field OK 0.06s
363/390 decodetree - qemu:succ_pattern_group_nest1 OK 0.06s
364/390 decodetree - qemu:succ_pattern_group_nest2 OK 0.06s
365/390 decodetree - qemu:succ_pattern_group_nest3 OK 0.06s
366/390 decodetree - qemu:succ_pattern_group_nest4 OK 0.06s
367/390 softfloat+softfloat-conv - qemu:fp-test-float-to-float OK 0.02s
368/390 softfloat+softfloat-conv - qemu:fp-test-int-to-float OK 0.01s
369/390 softfloat+softfloat-conv - qemu:fp-test-uint-to-float OK 0.01s
370/390 softfloat+softfloat-conv - qemu:fp-test-float-to-int OK 0.04s
371/390 softfloat+softfloat-conv - qemu:fp-test-float-to-uint OK 0.04s
372/390 softfloat+softfloat-conv - qemu:fp-test-round-to-integer OK 0.02s
373/390 softfloat+softfloat-compare - qemu:fp-test-eq_signaling OK 0.07s
374/390 softfloat+softfloat-compare - qemu:fp-test-le OK 0.08s
375/390 softfloat+softfloat-compare - qemu:fp-test-le_quiet OK 0.08s
376/390 softfloat+softfloat-compare - qemu:fp-test-lt_quiet OK 0.07s
377/390 softfloat+softfloat-ops - qemu:fp-test-add OK 0.81s
378/390 softfloat+softfloat-ops - qemu:fp-test-sub OK 0.81s
379/390 softfloat+softfloat-ops - qemu:fp-test-mul OK 4.12s
380/390 softfloat+softfloat-ops - qemu:fp-test-div OK 3.37s
381/390 softfloat+softfloat-ops - qemu:fp-test-rem OK 1.88s
382/390 softfloat+softfloat-ops - qemu:fp-test-sqrt OK 0.05s
383/390 softfloat+softfloat-ops - qemu:fp-test-log2 OK 0.02s
384/390 qapi-schema+qapi-frontend - qemu:QAPI schema regression tests OK 0.18s
385/390 tracetool - qemu:dtrace OK 0.38s
386/390 tracetool - qemu:ftrace OK 0.23s
387/390 tracetool - qemu:log OK 0.19s
388/390 tracetool - qemu:simple OK 0.20s
389/390 tracetool - qemu:syslog OK 0.21s
390/390 tracetool - qemu:ust OK 0.27s
Ok: 368
Fail: 0
Skipped: 22
Could you please confirm whether you are using the following repository and branch?
https://github.com/legoater/qemu , branch: aspeed-11.0
If so, I will use this code base and apply the patch series to run make check and try to reproduce the issue.
Thanks-Jamin
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-27 5:07 ` Jamin Lin
@ 2026-01-27 6:09 ` Jamin Lin
2026-01-27 9:48 ` Jamin Lin
0 siblings, 1 reply; 35+ messages in thread
From: Jamin Lin @ 2026-01-27 6:09 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
Hi Cédric
> Subject: RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> Hi Cédric
>
> > Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> > SDRAM remap
> >
> > On 1/20/26 10:29, Jamin Lin via qemu development wrote:
> > > This commit adds two MemoryRegion aliases to support PSP access to SSP
> > > SDRAM through shared memory remapping, as defined by the default SCU
> > > configuration.
> > >
> > > The SSP exposes two DRAM aliases:
> > > - remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM
> offset
> > 0x2000000
> > > - remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM
> offset
> > > 0x0
> > >
> > > These regions correspond to the default SCU register values, which
> > > control the mapping between PSP and coprocessor memory windows.
> > >
> > > Set SSP CPUID 4 and bumps the SCU VMState version to 3.
> > >
> > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > > ---
> > > include/hw/misc/aspeed_scu.h | 5 +++++
> > > hw/arm/aspeed_ast27x0-fc.c | 2 ++
> > > hw/arm/aspeed_ast27x0-ssp.c | 6 ++++++
> > > hw/arm/aspeed_ast27x0.c | 4 ++++
> > > hw/misc/aspeed_scu.c | 38
> > ++++++++++++++++++++++++++++++++++--
> > > 5 files changed, 53 insertions(+), 2 deletions(-)
> > make check fails with :
> >
> > Unexpected error in aspeed_scu_realize()
> at ../hw/misc/aspeed_scu.c:609:
> > qemu-system-aarch64: aspeed.scu: 'dram' link not set
> >
>
> Sorry, I cannot reproduce the issue on my side. My qemu version:
> https://github.com/qemu/qemu/commit/fea2d7a784fc3627a8aa72875f51fe76
> 34b04b81
>
> I tested on Ubuntu 24.04 and obtained the following results:
>
> Ok: 379
> Fail: 0
> Skipped: 14
>
> Full log written to
> /home/jamin_lin/qemu-work/debug-ssp-review/build/meson-logs/testlog.txt
>
> I also tested on Ubuntu 22.04 and got the same test results.
> (qemu) jamin@aspeed-fw01:~/qemu-work/build$ make check
> [1/48] Generating qemu-version.h with a custom command (wrapped by
> meson to capture output)
> [2/34] Generating tests/include/QAPI test (include) with a custom command
> /home/jamin/qemu-work/build/pyvenv/bin/meson test --no-rebuild -t 1
> --num-processes 1 --print-errorlogs --suite block --suite decodetree --suite
> func --suite func-aarch64 --suite func-arm --suite func-quick --suite
> qapi-frontend --suite qapi-interop --suite qapi-schema --suite qga --suite
> qtest --suite qtest-aarch64 --suite qtest-arm --suite slirp --suite softfloat
> --suite softfloat-compare --suite softfloat-conv --suite softfloat-ops --suite
> tracetool --suite unit
> 1/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bios-tables-test
> OK 92.91s 14 subtests passed
> 2/390 qtest+qtest-arm - qemu:qtest-arm/qom-test
> OK 110.65s 83 subtests passed
> 3/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qom-test
> OK 132.70s 93 subtests passed
> 4/390 qtest+qtest-arm - qemu:qtest-arm/device-introspect-test
> OK 12.61s 6 subtests passed
> 5/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/device-introspect-test
> OK 12.97s 6 subtests passed
> 6/390 qtest+qtest-arm - qemu:qtest-arm/cdrom-test
> SKIP 0.02s
> 7/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/cdrom-test
> SKIP 0.02s
> 8/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_usart-test
> OK 1.26s 7 subtests passed
> 9/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/migration-test
> OK 14.45s 8 subtests passed
> 10/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_smc-test
> OK 85.36s 34 subtests passed
> 11/390 qtest+qtest-arm - qemu:qtest-arm/boot-serial-test
> OK 0.89s 3 subtests passed
> 12/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/boot-serial-test
> OK 0.53s 1 subtests passed
> 13/390 unit - qemu:test-crypto-block
> SKIP 0.02s
> 14/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_pwm-test
> OK 11.35s 3 subtests passed
> 15/390 qtest+qtest-arm - qemu:qtest-arm/test-hmp
> OK 89.69s 84 subtests passed
> 16/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/test-hmp
> OK 102.52s 94 subtests passed
> 17/390 unit - qemu:test-aio-multithread
> OK 7.44s 6 subtests passed
> 18/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_watchdog_timer-test
> OK 6.56s 15 subtests passed
> 19/390 qtest+qtest-arm - qemu:qtest-arm/qmp-cmd-test
> OK 10.29s 64 subtests passed
> 20/390 qtest+qtest-arm - qemu:qtest-arm/qos-test
> OK 23.63s 97 subtests passed
> 21/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qmp-cmd-test
> OK 10.40s 64 subtests passed
> 22/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qos-test
> OK 33.04s 128 subtests passed
> 23/390 func-quick+func-arm - qemu:func-arm-migration
> OK 1.24s 2 subtests passed
> 24/390 func-quick+func-arm - qemu:func-arm-empty_cpu_model
> OK 0.23s 1 subtests passed
> 25/390 func-quick+func-arm - qemu:func-arm-info_usernet
> OK 0.29s 1 subtests passed
> 26/390 func-quick+func-arm - qemu:func-arm-linters
> SKIP 0.13s 0 subtests passed
> 27/390 func-quick+func-arm - qemu:func-arm-version
> OK 0.21s 1 subtests passed
> 28/390 func-quick+func-arm - qemu:func-arm-vnc
> SKIP 0.41s 0 subtests passed
> 29/390 func-quick+func-aarch64 - qemu:func-aarch64-migration
> OK 1.22s 2 subtests passed
> 30/390 func-quick+func-aarch64 - qemu:func-aarch64-vmstate
> SKIP 0.15s 0 subtests passed
> 31/390 func-quick+func-aarch64 - qemu:func-aarch64-empty_cpu_model
> OK 0.21s 1 subtests passed
> 32/390 func-quick+func-aarch64 - qemu:func-aarch64-info_usernet
> OK 0.28s 1 subtests passed
> 33/390 func-quick+func-aarch64 - qemu:func-aarch64-linters
> SKIP 0.13s 0 subtests passed
> 34/390 func-quick+func-aarch64 - qemu:func-aarch64-version
> OK 0.23s 1 subtests passed
> 35/390 func-quick+func-aarch64 - qemu:func-aarch64-vnc
> SKIP 0.42s 0 subtests passed
> 36/390 unit - qemu:test-replication
> OK 4.45s 13 subtests passed
> 37/390 unit - qemu:test-bufferiszero
> OK 1.10s 1 subtests passed
> 38/390 qtest+qtest-arm - qemu:qtest-arm/sse-timer-test
> OK 0.32s 3 subtests passed
> 39/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-dualtimer-test
> OK 0.17s 2 subtests passed
> 40/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-timer-test
> OK 0.18s 1 subtests passed
> 41/390 qtest+qtest-arm - qemu:qtest-arm/cmsdk-apb-watchdog-test
> OK 1.29s 7 subtests passed
> 42/390 qtest+qtest-arm - qemu:qtest-arm/pflash-cfi02-test
> OK 1.70s 4 subtests passed
> 43/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_gpio-test
> OK 0.48s 2 subtests passed
> 44/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_hace-test
> OK 9.99s 30 subtests passed
> 45/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_scu-test
> OK 1.29s 4 subtests passed
> 46/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_adc-test
> OK 2.89s 6 subtests passed
> 47/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_gpio-test
> OK 0.25s 18 subtests passed
> 48/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_rng-test
> OK 0.24s 2 subtests passed
> 49/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_sdhci-test
> OK 0.99s 3 subtests passed
> 50/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_smbus-test
> OK 8.79s 40 subtests passed
> 51/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_timer-test
> OK 0.35s 180 subtests passed
> 52/390 qtest+qtest-arm - qemu:qtest-arm/npcm7xx_emc-test
> OK 1.34s 6 subtests passed
> 53/390 qtest+qtest-arm - qemu:qtest-arm/hexloader-test
> OK 0.18s 1 subtests passed
> 54/390 qtest+qtest-arm - qemu:qtest-arm/tpm-tis-i2c-test
> OK 0.75s 6 subtests passed
> 55/390 qtest+qtest-arm - qemu:qtest-arm/test-arm-mptimer
> OK 0.22s 61 subtests passed
> 56/390 qtest+qtest-arm - qemu:qtest-arm/microbit-test
> OK 4.17s 6 subtests passed
> 57/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_exti-test
> OK 0.20s 9 subtests passed
> 58/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_syscfg-test
> OK 0.20s 10 subtests passed
> 59/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_rcc-test
> OK 0.19s 5 subtests passed
> 60/390 qtest+qtest-arm - qemu:qtest-arm/stm32l4x5_gpio-test
> OK 0.28s 14 subtests passed
> 61/390 qtest+qtest-arm - qemu:qtest-arm/aspeed_fsi-test
> OK 0.42s 4 subtests passed
> 62/390 qtest+qtest-arm - qemu:qtest-arm/dm163-test
> OK 0.58s 3 subtests passed
> 63/390 qtest+qtest-arm - qemu:qtest-arm/arm-cpu-features
> OK 0.55s 1 subtests passed
> 64/390 qtest+qtest-arm - qemu:qtest-arm/machine-none-test
> OK 0.16s 1 subtests passed
> 65/390 qtest+qtest-arm - qemu:qtest-arm/qmp-test
> OK 0.65s 4 subtests passed
> 66/390 qtest+qtest-arm - qemu:qtest-arm/readconfig-test
> OK 0.16s 1 subtests passed
> 67/390 qtest+qtest-arm - qemu:qtest-arm/netdev-socket
> OK 3.70s 10 subtests passed
> 68/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-device-test
> OK 0.22s 5 subtests passed
> 69/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-device-swtpm-test
> SKIP 0.02s 0 subtests passed
> 70/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/xlnx-canfd-test
> OK 2.48s 3 subtests passed
> 71/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/xlnx-versal-trng-test
> OK 0.85s 5 subtests passed
> 72/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bcm2835-dma-test
> OK 0.19s 1 subtests passed
> 73/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/bcm2835-i2c-test
> OK 0.19s 3 subtests passed
> 74/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/tpm-tis-i2c-test
> OK 0.76s 6 subtests passed
> 75/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-gpio-test
> OK 1.27s 2 subtests passed
> 76/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-hace-test
> OK 6.53s 11 subtests passed
> 77/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-sgpio-test
> OK 11.10s 3 subtests passed
> 78/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/ast2700-smc-test
> OK 2.39s 8 subtests passed
> 79/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/npcm_gmac-test
> OK 1.00s 4 subtests passed
> 80/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/iommu-smmuv3-test
> OK 0.77s 3 subtests passed
> 81/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/cxl-test
> OK 0.28s 1 subtests passed
> 82/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/arm-cpu-features
> OK 1.19s 3 subtests passed
> 83/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/numa-test
> OK 1.16s 5 subtests passed
> 84/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/machine-none-test
> OK 0.16s 1 subtests passed
> 85/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/qmp-test
> OK 0.66s 4 subtests passed
> 86/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/readconfig-test
> OK 0.16s 1 subtests passed
> 87/390 qtest+qtest-aarch64 - qemu:qtest-aarch64/netdev-socket
> OK 3.71s 10 subtests passed
> 88/390 unit - qemu:check-block-qdict
> OK 0.02s 10 subtests passed
> 89/390 unit - qemu:check-qdict
> OK 0.02s 15 subtests passed
> 90/390 unit - qemu:check-qnum
> OK 0.01s 8 subtests passed
> 91/390 unit - qemu:check-qstring
> OK 0.01s 4 subtests passed
> 92/390 unit - qemu:check-qlist
> OK 0.01s 4 subtests passed
> 93/390 unit - qemu:check-qnull
> OK 0.01s 2 subtests passed
> 94/390 unit - qemu:check-qobject
> OK 0.01s 7 subtests passed
> 95/390 unit - qemu:check-qjson
> OK 0.42s 31 subtests passed
> 96/390 unit - qemu:check-qlit
> OK 0.01s 2 subtests passed
> 97/390 unit - qemu:test-error-report
> OK 0.04s 5 subtests passed
> 98/390 unit - qemu:test-qobject-output-visitor
> OK 0.02s 16 subtests passed
> 99/390 unit - qemu:test-clone-visitor
> OK 0.02s 7 subtests passed
> 100/390 unit - qemu:test-qobject-input-visitor
> OK 0.02s 42 subtests passed
> 101/390 unit - qemu:test-forward-visitor
> OK 0.02s 7 subtests passed
> 102/390 unit - qemu:test-string-input-visitor
> OK 0.04s 8 subtests passed
> 103/390 unit - qemu:test-string-output-visitor
> OK 0.02s 14 subtests passed
> 104/390 unit - qemu:test-visitor-serialization
> OK 0.03s 156 subtests passed
> 105/390 unit - qemu:test-bitmap
> OK 0.01s 2 subtests passed
> 106/390 unit - qemu:test-resv-mem
> OK 0.01s 3 subtests passed
> 107/390 unit - qemu:test-x86-topo
> OK 0.01s 1 subtests passed
> 108/390 unit - qemu:test-cutils
> OK 0.02s 179 subtests passed
> 109/390 unit - qemu:test-div128
> OK 0.01s 2 subtests passed
> 110/390 unit - qemu:test-shift128
> OK 0.02s 2 subtests passed
> 111/390 unit - qemu:test-mul64
> OK 0.02s 2 subtests passed
> 112/390 unit - qemu:test-int128
> OK 0.02s 11 subtests passed
> 113/390 unit - qemu:rcutorture
> OK 2.03s 2 subtests passed
> 114/390 unit - qemu:test-rcu-list
> OK 4.03s 3 subtests passed
> 115/390 unit - qemu:test-rcu-simpleq
> OK 4.03s 3 subtests passed
> 116/390 unit - qemu:test-rcu-tailq
> OK 4.03s 3 subtests passed
> 117/390 unit - qemu:test-rcu-slist
> OK 4.04s 3 subtests passed
> 118/390 unit - qemu:test-qdist
> OK 0.02s 8 subtests passed
> 119/390 unit - qemu:test-qht
> OK 0.64s 2 subtests passed
> 120/390 unit - qemu:test-qtree
> OK 0.02s 4 subtests passed
> 121/390 unit - qemu:test-bitops
> OK 0.02s 6 subtests passed
> 122/390 unit - qemu:test-bitcnt
> OK 0.02s 4 subtests passed
> 123/390 unit - qemu:test-qgraph
> OK 0.02s 23 subtests passed
> 124/390 unit - qemu:check-qom-interface
> OK 0.02s 2 subtests passed
> 125/390 unit - qemu:check-qom-proplist
> OK 0.02s 9 subtests passed
> 126/390 unit - qemu:test-qemu-opts
> OK 0.02s 19 subtests passed
> 127/390 unit - qemu:test-keyval
> OK 0.02s 13 subtests passed
> 128/390 unit - qemu:test-logging
> OK 0.03s 4 subtests passed
> 129/390 unit - qemu:test-qapi-util
> OK 0.02s 2 subtests passed
> 130/390 unit - qemu:test-interval-tree
> OK 0.01s 6 subtests passed
> 131/390 unit - qemu:test-fifo
> OK 0.01s 10 subtests passed
> 132/390 unit - qemu:test-qmp-event
> OK 0.02s 6 subtests passed
> 133/390 unit - qemu:test-coroutine
> OK 0.02s 12 subtests passed
> 134/390 unit - qemu:test-aio
> OK 3.53s 27 subtests passed
> 135/390 unit - qemu:test-throttle
> OK 0.02s 17 subtests passed
> 136/390 unit - qemu:test-thread-pool
> OK 4.04s 6 subtests passed
> 137/390 unit - qemu:test-hbitmap
> OK 0.24s 40 subtests passed
> 138/390 unit - qemu:test-bdrv-drain
> OK 0.12s 30 subtests passed
> 139/390 unit - qemu:test-bdrv-graph-mod
> OK 0.02s 5 subtests passed
> 140/390 unit - qemu:test-blockjob
> OK 0.02s 8 subtests passed
> 141/390 unit - qemu:test-blockjob-txn
> OK 0.02s 7 subtests passed
> 142/390 unit - qemu:test-block-backend
> OK 0.01s 2 subtests passed
> 143/390 unit - qemu:test-block-iothread
> OK 0.04s 22 subtests passed
> 144/390 unit - qemu:test-write-threshold
> OK 0.02s 2 subtests passed
> 145/390 unit - qemu:test-crypto-hash
> OK 0.02s 6 subtests passed
> 146/390 unit - qemu:test-crypto-hmac
> OK 0.02s 4 subtests passed
> 147/390 unit - qemu:test-crypto-cipher
> SKIP 0.02s
> 148/390 unit - qemu:test-crypto-akcipher
> OK 0.02s 16 subtests passed
> 149/390 unit - qemu:test-crypto-secret
> OK 0.01s 10 subtests passed
> 150/390 unit - qemu:test-crypto-der
> OK 0.01s 4 subtests passed
> 151/390 unit - qemu:test-authz-simple
> OK 0.02s 1 subtests passed
> 152/390 unit - qemu:test-authz-list
> OK 0.02s 6 subtests passed
> 153/390 unit - qemu:test-authz-listfile
> OK 0.02s 5 subtests passed
> 154/390 unit - qemu:test-io-task
> OK 0.02s 5 subtests passed
> 155/390 unit - qemu:test-io-channel-socket
> OK 0.10s 9 subtests passed
> 156/390 unit - qemu:test-io-channel-file
> OK 0.04s 5 subtests passed
> 157/390 unit - qemu:test-io-channel-command
> OK 0.21s 4 subtests passed
> 158/390 unit - qemu:test-io-channel-buffer
> OK 0.03s 1 subtests passed
> 159/390 unit - qemu:test-io-channel-null
> OK 0.02s 1 subtests passed
> 160/390 unit - qemu:test-crypto-ivgen
> OK 0.02s 9 subtests passed
> 161/390 unit - qemu:test-crypto-afsplit
> OK 0.05s 4 subtests passed
> 162/390 unit - qemu:test-timed-average
> OK 0.02s 1 subtests passed
> 163/390 unit - qemu:test-uuid
> OK 0.02s 6 subtests passed
> 164/390 unit - qemu:test-image-locking
> OK 0.02s 2 subtests passed
> 165/390 unit - qemu:test-nested-aio-poll
> OK 0.01s 1 subtests passed
> 166/390 unit - qemu:test-crypto-pbkdf
> SKIP 0.02s
> 167/390 unit - qemu:ptimer-test
> OK 0.04s 576 subtests passed
> 168/390 unit - qemu:test-iov
> OK 0.59s 6 subtests passed
> 169/390 unit - qemu:test-opts-visitor
> OK 0.05s 33 subtests passed
> 170/390 unit - qemu:test-xs-node
> OK 0.01s 7 subtests passed
> 171/390 unit - qemu:test-virtio-dmabuf
> OK 0.01s 5 subtests passed
> 172/390 unit - qemu:test-qmp-cmds
> OK 0.01s 10 subtests passed
> 173/390 unit - qemu:test-xbzrle
> OK 0.04s 6 subtests passed
> 174/390 unit - qemu:test-util-sockets
> OK 0.01s 21 subtests passed
> 175/390 unit - qemu:test-base64
> OK 0.02s 4 subtests passed
> 176/390 unit - qemu:test-smp-parse
> OK 0.03s 10 subtests passed
> 177/390 unit - qemu:test-vmstate
> OK 0.02s 23 subtests passed
> 178/390 unit - qemu:test-yank
> OK 0.02s 6 subtests passed
> 179/390 unit - qemu:test-util-filemonitor
> OK 0.06s 1 subtests passed
> 180/390 unit - qemu:test-char
> OK 2.13s 40 subtests passed
> 181/390 unit - qemu:test-qdev-global-props
> OK 0.04s 4 subtests passed
> 182/390 unit - qemu:test-qga
> OK 4.18s 29 subtests passed
> 183/390 slirp:ping
> OK 0.12s
> 184/390 slirp:ncsi
> OK 0.02s
> 185/390 unit+qga - qemu:qga-ssh-test
> OK 0.03s
> 186/390 unit - qemu:xml-preprocess
> OK 0.23s
> 187/390 qapi-schema+qapi-interop - qemu:QAPI firmware.json regression test
> OK 0.09s
> 188/390 qapi-schema+qapi-interop - qemu:QAPI vhost-user.json regression test
> OK 0.09s
> 189/390 block - qemu:io-qcow2-001
> OK 1.23s 1 subtests passed
> 190/390 block - qemu:io-qcow2-002
> OK 1.48s 1 subtests passed
> 191/390 block - qemu:io-qcow2-003
> OK 1.24s 1 subtests passed
> 192/390 block - qemu:io-qcow2-004
> OK 0.49s 1 subtests passed
> 193/390 block - qemu:io-qcow2-005
> OK 0.47s 1 subtests passed
> 194/390 block - qemu:io-qcow2-007
> OK 1.46s 1 subtests passed
> 195/390 block - qemu:io-qcow2-008
> OK 1.21s 1 subtests passed
> 196/390 block - qemu:io-qcow2-009
> OK 0.38s 1 subtests passed
> 197/390 block - qemu:io-qcow2-010
> OK 0.39s 1 subtests passed
> 198/390 block - qemu:io-qcow2-011
> OK 0.68s 1 subtests passed
> 199/390 block - qemu:io-qcow2-012
> OK 0.34s 1 subtests passed
> 200/390 block - qemu:io-qcow2-013
> OK 7.30s 1 subtests passed
> 201/390 block - qemu:io-qcow2-017
> OK 0.99s 1 subtests passed
> 202/390 block - qemu:io-qcow2-018
> OK 0.97s 1 subtests passed
> 203/390 block - qemu:io-qcow2-019
> OK 1.52s 1 subtests passed
> 204/390 block - qemu:io-qcow2-020
> OK 1.98s 1 subtests passed
> 205/390 block - qemu:io-qcow2-021
> OK 0.86s 1 subtests passed
> 206/390 block - qemu:io-qcow2-022
> OK 1.76s 1 subtests passed
> 207/390 block - qemu:io-qcow2-024
> OK 3.59s 1 subtests passed
> 208/390 block - qemu:io-qcow2-025
> OK 1.78s 1 subtests passed
> 209/390 block - qemu:io-qcow2-027
> OK 0.42s 1 subtests passed
> 210/390 block - qemu:io-qcow2-029
> OK 1.02s 1 subtests passed
> 211/390 block - qemu:io-qcow2-031
> OK 0.95s 1 subtests passed
> 212/390 block - qemu:io-qcow2-032
> OK 0.43s 1 subtests passed
> 213/390 block - qemu:io-qcow2-033
> OK 1.78s 1 subtests passed
> 214/390 block - qemu:io-qcow2-034
> OK 1.66s 1 subtests passed
> 215/390 block - qemu:io-qcow2-035
> OK 0.69s 1 subtests passed
> 216/390 block - qemu:io-qcow2-036
> OK 1.72s 1 subtests passed
> 217/390 block - qemu:io-qcow2-037
> OK 1.52s 1 subtests passed
> 218/390 block - qemu:io-qcow2-038
> OK 0.96s 1 subtests passed
> 219/390 block - qemu:io-qcow2-039
> OK 1.93s 1 subtests passed
> 220/390 block - qemu:io-qcow2-040
> OK 11.63s 1 subtests passed
> 221/390 block - qemu:io-qcow2-041
> OK 20.36s 1 subtests passed
> 222/390 block - qemu:io-qcow2-042
> OK 0.48s 1 subtests passed
> 223/390 block - qemu:io-qcow2-043
> OK 1.40s 1 subtests passed
> 224/390 block - qemu:io-qcow2-046
> OK 0.57s 1 subtests passed
> 225/390 block - qemu:io-qcow2-047
> OK 0.36s 1 subtests passed
> 226/390 block - qemu:io-qcow2-048
> OK 0.73s 1 subtests passed
> 227/390 block - qemu:io-qcow2-049
> SKIP 0.25s 0 subtests passed
> 228/390 block - qemu:io-qcow2-050
> OK 0.65s 1 subtests passed
> 229/390 block - qemu:io-qcow2-052
> OK 1.15s 1 subtests passed
> 230/390 block - qemu:io-qcow2-053
> OK 0.42s 1 subtests passed
> 231/390 block - qemu:io-qcow2-054
> OK 0.48s 1 subtests passed
> 232/390 block - qemu:io-qcow2-060
> OK 5.65s 1 subtests passed
> 233/390 block - qemu:io-qcow2-061
> OK 6.55s 1 subtests passed
> 234/390 block - qemu:io-qcow2-062
> OK 0.40s 1 subtests passed
> 235/390 block - qemu:io-qcow2-063
> OK 1.08s 1 subtests passed
> 236/390 block - qemu:io-qcow2-066
> OK 1.35s 1 subtests passed
> 237/390 block - qemu:io-qcow2-069
> OK 0.45s 1 subtests passed
> 238/390 block - qemu:io-qcow2-071
> OK 1.25s 1 subtests passed
> 239/390 block - qemu:io-qcow2-072
> OK 0.42s 1 subtests passed
> 240/390 block - qemu:io-qcow2-073
> OK 1.83s 1 subtests passed
> 241/390 block - qemu:io-qcow2-074
> OK 0.65s 1 subtests passed
> 242/390 block - qemu:io-qcow2-079
> OK 1.56s 1 subtests passed
> 243/390 block - qemu:io-qcow2-080
> OK 12.02s 1 subtests passed
> 244/390 block - qemu:io-qcow2-086
> OK 0.46s 1 subtests passed
> 245/390 block - qemu:io-qcow2-089
> OK 0.82s 1 subtests passed
> 246/390 block - qemu:io-qcow2-090
> OK 0.38s 1 subtests passed
> 247/390 block - qemu:io-qcow2-097
> OK 2.60s 1 subtests passed
> 248/390 block - qemu:io-qcow2-098
> OK 1.39s 1 subtests passed
> 249/390 block - qemu:io-qcow2-099
> OK 0.97s 1 subtests passed
> 250/390 block - qemu:io-qcow2-103
> OK 0.70s 1 subtests passed
> 251/390 block - qemu:io-qcow2-104
> OK 0.50s 1 subtests passed
> 252/390 block - qemu:io-qcow2-105
> OK 0.60s 1 subtests passed
> 253/390 block - qemu:io-qcow2-107
> OK 0.36s 1 subtests passed
> 254/390 block - qemu:io-qcow2-108
> SKIP 0.29s 0 subtests passed
> 255/390 block - qemu:io-qcow2-110
> OK 0.66s 1 subtests passed
> 256/390 block - qemu:io-qcow2-111
> OK 0.29s 1 subtests passed
> 257/390 block - qemu:io-qcow2-114
> OK 0.81s 1 subtests passed
> 258/390 block - qemu:io-qcow2-117
> OK 0.78s 1 subtests passed
> 259/390 block - qemu:io-qcow2-120
> OK 0.50s 1 subtests passed
> 260/390 block - qemu:io-qcow2-126
> OK 0.86s 1 subtests passed
> 261/390 block - qemu:io-qcow2-127
> OK 1.25s 1 subtests passed
> 262/390 block - qemu:io-qcow2-133
> OK 0.70s 1 subtests passed
> 263/390 block - qemu:io-qcow2-134
> SKIP 0.25s 0 subtests passed
> 264/390 block - qemu:io-qcow2-137
> OK 1.35s 1 subtests passed
> 265/390 block - qemu:io-qcow2-138
> OK 0.59s 1 subtests passed
> 266/390 block - qemu:io-qcow2-140
> OK 0.78s 1 subtests passed
> 267/390 block - qemu:io-qcow2-141
> OK 0.72s 1 subtests passed
> 268/390 block - qemu:io-qcow2-143
> OK 0.50s 1 subtests passed
> 269/390 block - qemu:io-qcow2-150
> OK 0.32s 1 subtests passed
> 270/390 block - qemu:io-qcow2-154
> OK 7.65s 1 subtests passed
> 271/390 block - qemu:io-qcow2-156
> OK 2.00s 1 subtests passed
> 272/390 block - qemu:io-qcow2-158
> SKIP 0.24s 0 subtests passed
> 273/390 block - qemu:io-qcow2-159
> OK 16.99s 1 subtests passed
> 274/390 block - qemu:io-qcow2-161
> OK 2.87s 1 subtests passed
> 275/390 block - qemu:io-qcow2-170
> OK 0.55s 1 subtests passed
> 276/390 block - qemu:io-qcow2-172
> SKIP 0.25s 0 subtests passed
> 277/390 block - qemu:io-qcow2-174
> OK 0.35s 1 subtests passed
> 278/390 block - qemu:io-qcow2-176
> OK 5.97s 1 subtests passed
> 279/390 block - qemu:io-qcow2-177
> OK 1.94s 1 subtests passed
> 280/390 block - qemu:io-qcow2-179
> OK 1.28s 1 subtests passed
> 281/390 block - qemu:io-qcow2-181
> SKIP 0.74s 0 subtests passed
> 282/390 block - qemu:io-qcow2-184
> OK 0.71s 1 subtests passed
> 283/390 block - qemu:io-qcow2-186
> SKIP 0.33s 0 subtests passed
> 284/390 block - qemu:io-qcow2-187
> OK 0.47s 1 subtests passed
> 285/390 block - qemu:io-qcow2-190
> OK 4.16s 1 subtests passed
> 286/390 block - qemu:io-qcow2-191
> OK 38.33s 1 subtests passed
> 287/390 block - qemu:io-qcow2-192
> SKIP 0.23s 0 subtests passed
> 288/390 block - qemu:io-qcow2-195
> OK 0.82s 1 subtests passed
> 289/390 block - qemu:io-qcow2-203
> OK 0.52s 1 subtests passed
> 290/390 block - qemu:io-qcow2-214
> OK 1.57s 1 subtests passed
> 291/390 block - qemu:io-qcow2-217
> OK 0.48s 1 subtests passed
> 292/390 block - qemu:io-qcow2-220
> SKIP 0.25s 0 subtests passed
> 293/390 block - qemu:io-qcow2-226
> OK 0.37s 1 subtests passed
> 294/390 block - qemu:io-qcow2-229
> OK 0.95s 1 subtests passed
> 295/390 block - qemu:io-qcow2-244
> OK 3.16s 1 subtests passed
> 296/390 block - qemu:io-qcow2-249
> OK 1.16s 1 subtests passed
> 297/390 block - qemu:io-qcow2-251
> OK 1.64s 1 subtests passed
> 298/390 block - qemu:io-qcow2-252
> OK 0.61s 1 subtests passed
> 299/390 block - qemu:io-qcow2-256
> OK 0.66s 1 subtests passed
> 300/390 block - qemu:io-qcow2-265
> OK 0.45s 1 subtests passed
> 301/390 block - qemu:io-qcow2-267
> OK 3.34s 1 subtests passed
> 302/390 block - qemu:io-qcow2-268
> OK 0.35s 1 subtests passed
> 303/390 block - qemu:io-qcow2-271
> OK 26.94s 1 subtests passed
> 304/390 block - qemu:io-qcow2-283
> OK 1.23s 1 subtests passed
> 305/390 block - qemu:io-qcow2-287
> SKIP 0.41s 0 subtests passed
> 306/390 block - qemu:io-qcow2-290
> OK 1.08s 1 subtests passed
> 307/390 block - qemu:io-qcow2-292
> OK 0.56s 1 subtests passed
> 308/390 block - qemu:io-qcow2-299
> OK 0.46s 1 subtests passed
> 309/390 block - qemu:io-qcow2-313
> OK 0.60s 1 subtests passed
> 310/390 block - qemu:io-qcow2-314
> OK 4.91s 1 subtests passed
> 311/390 block - qemu:io-qcow2-copy-before-write
> OK 4.50s 1 subtests passed
> 312/390 block - qemu:io-qcow2-detect-zeroes-registered-buf
> OK 0.35s 1 subtests passed
> 313/390 block - qemu:io-qcow2-iothreads-commit-active
> OK 0.68s 1 subtests passed
> 314/390 block - qemu:io-qcow2-iothreads-resize
> OK 0.47s 1 subtests passed
> 315/390 block - qemu:io-qcow2-iothreads-stream
> OK 0.77s 1 subtests passed
> 316/390 block - qemu:io-qcow2-mirror-sparse
> OK 6.94s 1 subtests passed
> 317/390 block - qemu:io-qcow2-nbd-multiconn
> SKIP 0.27s 0 subtests passed
> 318/390 block - qemu:io-qcow2-nbd-qemu-allocation
> OK 0.56s 1 subtests passed
> 319/390 block - qemu:io-qcow2-qemu-img-close-errors
> OK 2.00s 1 subtests passed
> 320/390 block - qemu:io-qcow2-qsd-jobs
> OK 0.47s 1 subtests passed
> 321/390 block - qemu:io-qcow2-regression-vhdx-log
> OK 0.41s 1 subtests passed
> 322/390 decodetree - qemu:err_argset1
> OK 0.05s
> 323/390 decodetree - qemu:err_argset2
> OK 0.05s
> 324/390 decodetree - qemu:err_field1
> OK 0.05s
> 325/390 decodetree - qemu:err_field2
> OK 0.04s
> 326/390 decodetree - qemu:err_field3
> OK 0.04s
> 327/390 decodetree - qemu:err_field4
> OK 0.06s
> 328/390 decodetree - qemu:err_field5
> OK 0.06s
> 329/390 decodetree - qemu:err_field6
> OK 0.05s
> 330/390 decodetree - qemu:err_field7
> OK 0.05s
> 331/390 decodetree - qemu:err_field8
> OK 0.05s
> 332/390 decodetree - qemu:err_field9
> OK 0.05s
> 333/390 decodetree - qemu:err_field10
> OK 0.04s
> 334/390 decodetree - qemu:err_init1
> OK 0.04s
> 335/390 decodetree - qemu:err_init2
> OK 0.05s
> 336/390 decodetree - qemu:err_init3
> OK 0.05s
> 337/390 decodetree - qemu:err_init4
> OK 0.05s
> 338/390 decodetree - qemu:err_overlap1
> OK 0.06s
> 339/390 decodetree - qemu:err_overlap2
> OK 0.06s
> 340/390 decodetree - qemu:err_overlap3
> OK 0.06s
> 341/390 decodetree - qemu:err_overlap4
> OK 0.05s
> 342/390 decodetree - qemu:err_overlap5
> OK 0.05s
> 343/390 decodetree - qemu:err_overlap6
> OK 0.06s
> 344/390 decodetree - qemu:err_overlap7
> OK 0.06s
> 345/390 decodetree - qemu:err_overlap8
> OK 0.04s
> 346/390 decodetree - qemu:err_overlap9
> OK 0.06s
> 347/390 decodetree - qemu:err_pattern_group_empty
> OK 0.06s
> 348/390 decodetree - qemu:err_pattern_group_ident1
> OK 0.05s
> 349/390 decodetree - qemu:err_pattern_group_ident2
> OK 0.05s
> 350/390 decodetree - qemu:err_pattern_group_nest1
> OK 0.06s
> 351/390 decodetree - qemu:err_pattern_group_nest2
> OK 0.06s
> 352/390 decodetree - qemu:err_pattern_group_nest3
> OK 0.05s
> 353/390 decodetree - qemu:err_pattern_group_overlap1
> OK 0.05s
> 354/390 decodetree - qemu:err_width1
> OK 0.04s
> 355/390 decodetree - qemu:err_width2
> OK 0.04s
> 356/390 decodetree - qemu:err_width3
> OK 0.05s
> 357/390 decodetree - qemu:err_width4
> OK 0.05s
> 358/390 decodetree - qemu:succ_argset_type1
> OK 0.05s
> 359/390 decodetree - qemu:succ_function
> OK 0.05s
> 360/390 decodetree - qemu:succ_ident1
> OK 0.05s
> 361/390 decodetree - qemu:succ_infer1
> OK 0.05s
> 362/390 decodetree - qemu:succ_named_field
> OK 0.06s
> 363/390 decodetree - qemu:succ_pattern_group_nest1
> OK 0.06s
> 364/390 decodetree - qemu:succ_pattern_group_nest2
> OK 0.06s
> 365/390 decodetree - qemu:succ_pattern_group_nest3
> OK 0.06s
> 366/390 decodetree - qemu:succ_pattern_group_nest4
> OK 0.06s
> 367/390 softfloat+softfloat-conv - qemu:fp-test-float-to-float
> OK 0.02s
> 368/390 softfloat+softfloat-conv - qemu:fp-test-int-to-float
> OK 0.01s
> 369/390 softfloat+softfloat-conv - qemu:fp-test-uint-to-float
> OK 0.01s
> 370/390 softfloat+softfloat-conv - qemu:fp-test-float-to-int
> OK 0.04s
> 371/390 softfloat+softfloat-conv - qemu:fp-test-float-to-uint
> OK 0.04s
> 372/390 softfloat+softfloat-conv - qemu:fp-test-round-to-integer
> OK 0.02s
> 373/390 softfloat+softfloat-compare - qemu:fp-test-eq_signaling
> OK 0.07s
> 374/390 softfloat+softfloat-compare - qemu:fp-test-le
> OK 0.08s
> 375/390 softfloat+softfloat-compare - qemu:fp-test-le_quiet
> OK 0.08s
> 376/390 softfloat+softfloat-compare - qemu:fp-test-lt_quiet
> OK 0.07s
> 377/390 softfloat+softfloat-ops - qemu:fp-test-add
> OK 0.81s
> 378/390 softfloat+softfloat-ops - qemu:fp-test-sub
> OK 0.81s
> 379/390 softfloat+softfloat-ops - qemu:fp-test-mul
> OK 4.12s
> 380/390 softfloat+softfloat-ops - qemu:fp-test-div
> OK 3.37s
> 381/390 softfloat+softfloat-ops - qemu:fp-test-rem
> OK 1.88s
> 382/390 softfloat+softfloat-ops - qemu:fp-test-sqrt
> OK 0.05s
> 383/390 softfloat+softfloat-ops - qemu:fp-test-log2
> OK 0.02s
> 384/390 qapi-schema+qapi-frontend - qemu:QAPI schema regression tests
> OK 0.18s
> 385/390 tracetool - qemu:dtrace
> OK 0.38s
> 386/390 tracetool - qemu:ftrace
> OK 0.23s
> 387/390 tracetool - qemu:log
> OK 0.19s
> 388/390 tracetool - qemu:simple
> OK 0.20s
> 389/390 tracetool - qemu:syslog
> OK 0.21s
> 390/390 tracetool - qemu:ust
> OK 0.27s
>
> Ok: 368
> Fail: 0
> Skipped: 22
>
> Could you please confirm whether you are using the following repository and
> branch?
> https://github.com/legoater/qemu , branch: aspeed-11.0
>
I can reproduce this issue in https://github.com/legoater/qemu (aspeed-11.0)
I am analyzing this issue.
Thanks-Jamin
> If so, I will use this code base and apply the patch series to run make check
> and try to reproduce the issue.
>
> Thanks-Jamin
>
> > Thanks,
> >
> > C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-27 6:09 ` Jamin Lin
@ 2026-01-27 9:48 ` Jamin Lin
2026-02-02 6:57 ` Kane Chen
0 siblings, 1 reply; 35+ messages in thread
From: Jamin Lin @ 2026-01-27 9:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Kane Chen
Hi Cédric
> Subject: RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> I can reproduce this issue in https://github.com/legoater/qemu (aspeed-11.0) I
> am analyzing this issue.
>
Due to our mail server not updating DKIM (DomainKeys Identified Mail) signatures yet,
I am sending this update to inform you that the following patches are ready for review.
1. Resend v2
[PATCH v2 00/11] Add SSP/TSP power control and DRAM remap support for AST2700
https://patchew.org/QEMU/20260127092943.3731635-1-jamin._5Flin@aspeedtech.com/
2.
[PATCH v1 0/7] Update functional tests for AST2500/AST2600/AST103/AST1060
https://patchew.org/QEMU/20260127032348.2238527-1-jamin._5Flin@aspeedtech.com/
Thanks-Jamin
> Thanks-Jamin
>
> > If so, I will use this code base and apply the patch series to run
> > make check and try to reproduce the issue.
> >
> > Thanks-Jamin
> >
> > > Thanks,
> > >
> > > C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-01-27 9:48 ` Jamin Lin
@ 2026-02-02 6:57 ` Kane Chen
2026-02-02 9:33 ` Cédric Le Goater
0 siblings, 1 reply; 35+ messages in thread
From: Kane Chen @ 2026-02-02 6:57 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
> -----Original Message-----
> From: Jamin Lin <jamin_lin@aspeedtech.com>
> Sent: Tuesday, January 27, 2026 5:49 PM
> To: Cédric Le Goater <clg@kaod.org>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Andrew Jeffery <andrew@codeconstruct.com.au>;
> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Kane Chen
> <kane_chen@aspeedtech.com>
> Subject: RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> Hi Cédric
>
> > Subject: RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> > SDRAM remap
> >
> > I can reproduce this issue in https://github.com/legoater/qemu
> > (aspeed-11.0) I am analyzing this issue.
> >
>
> Due to our mail server not updating DKIM (DomainKeys Identified Mail)
> signatures yet, I am sending this update to inform you that the following
> patches are ready for review.
>
> 1. Resend v2
> [PATCH v2 00/11] Add SSP/TSP power control and DRAM remap support for
> AST2700
> https://patchew.org/QEMU/20260127092943.3731635-1-jamin._5Flin@aspe
> edtech.com/
>
> 2.
> [PATCH v1 0/7] Update functional tests for
> AST2500/AST2600/AST103/AST1060
> https://patchew.org/QEMU/20260127032348.2238527-1-jamin._5Flin@aspe
> edtech.com/
>
> Thanks-Jamin
>
> > Thanks-Jamin
> >
> > > If so, I will use this code base and apply the patch series to run
> > > make check and try to reproduce the issue.
> > >
> > > Thanks-Jamin
> > >
> > > > Thanks,
> > > >
> > > > C.
Hi Cédric,
Working with our IT team, we've transitioned to a Microsoft mail
server to ensure DKIM is correctly included. Could you please confirm
if you've received the below patch series?
https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA@SE3PR06MB8199.apcprd06.prod.outlook.com/
Best Regards,
Kane
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-02 6:57 ` Kane Chen
@ 2026-02-02 9:33 ` Cédric Le Goater
2026-02-02 9:46 ` Kane Chen
0 siblings, 1 reply; 35+ messages in thread
From: Cédric Le Goater @ 2026-02-02 9:33 UTC (permalink / raw)
To: Kane Chen, Jamin Lin, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi,
> Working with our IT team, we've transitioned to a Microsoft mail
> server to ensure DKIM is correctly included. Could you please confirm
> if you've received the below patch series?
>
> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA@SE3PR06MB8199.apcprd06.prod.outlook.com/
I did. Although, the series is not threaded. Probably due to the way
it was sent.
Thanks,
C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-02 9:33 ` Cédric Le Goater
@ 2026-02-02 9:46 ` Kane Chen
2026-02-02 10:48 ` Cédric Le Goater
0 siblings, 1 reply; 35+ messages in thread
From: Kane Chen @ 2026-02-02 9:46 UTC (permalink / raw)
To: Cédric Le Goater, Jamin Lin, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, February 2, 2026 5:34 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> Hi,
>
> > Working with our IT team, we've transitioned to a Microsoft mail
> > server to ensure DKIM is correctly included. Could you please confirm
> > if you've received the below patch series?
> >
> >
> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA
> @SE3PR0
> > 6MB8199.apcprd06.prod.outlook.com/
>
> I did. Although, the series is not threaded. Probably due to the way it was sent.
>
> Thanks,
>
> C.
Hi Cédric,
Thanks for the confirmation.
It's possible that the threading issue was related to some extra 'From' info in the
mail body. I've updated the script to remove it, so we'll see if that fixes the issue in
the next version.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-02 9:46 ` Kane Chen
@ 2026-02-02 10:48 ` Cédric Le Goater
2026-02-03 10:23 ` Kane Chen
0 siblings, 1 reply; 35+ messages in thread
From: Cédric Le Goater @ 2026-02-02 10:48 UTC (permalink / raw)
To: Kane Chen, Jamin Lin, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
On 2/2/26 10:46, Kane Chen wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Monday, February 2, 2026 5:34 PM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
>> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
>> list:All patches CC here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>
>> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
>> SDRAM remap
>>
>> Hi,
>>
>>> Working with our IT team, we've transitioned to a Microsoft mail
>>> server to ensure DKIM is correctly included. Could you please confirm
>>> if you've received the below patch series?
>>>
>>>
>> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA
>> @SE3PR0
>>> 6MB8199.apcprd06.prod.outlook.com/
>>
>> I did. Although, the series is not threaded. Probably due to the way it was sent.
>>
>> Thanks,
>>
>> C.
>
> Hi Cédric,
>
> Thanks for the confirmation.
>
> It's possible that the threading issue was related to some extra 'From' info in the
> mail body. I've updated the script to remove it, so we'll see if that fixes the issue in
> the next version.
OK. I can not fetch the series with b4. So you will have to resend.
What about the v6 of "hw/arm/aspeed: AST1700 LTPI support and device
hookups". Do you plan to resend soon ?
Thanks,
C.
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-02 10:48 ` Cédric Le Goater
@ 2026-02-03 10:23 ` Kane Chen
2026-02-03 12:56 ` Cédric Le Goater
0 siblings, 1 reply; 35+ messages in thread
From: Kane Chen @ 2026-02-03 10:23 UTC (permalink / raw)
To: Cédric Le Goater, Jamin Lin, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, February 2, 2026 6:49 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> On 2/2/26 10:46, Kane Chen wrote:
> >> -----Original Message-----
> >> From: Cédric Le Goater <clg@kaod.org>
> >> Sent: Monday, February 2, 2026 5:34 PM
> >> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> >> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> >> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee
> <leetroy@gmail.com>;
> >> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> >> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> >> list:All patches CC here <qemu-devel@nongnu.org>
> >> Cc: Troy Lee <troy_lee@aspeedtech.com>
> >> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> >> SDRAM remap
> >>
> >> Hi,
> >>
> >>> Working with our IT team, we've transitioned to a Microsoft mail
> >>> server to ensure DKIM is correctly included. Could you please
> >>> confirm if you've received the below patch series?
> >>>
> >>>
> >>
> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA
> >> @SE3PR0
> >>> 6MB8199.apcprd06.prod.outlook.com/
> >>
> >> I did. Although, the series is not threaded. Probably due to the way it was
> sent.
> >>
> >> Thanks,
> >>
> >> C.
> >
> > Hi Cédric,
> >
> > Thanks for the confirmation.
> >
> > It's possible that the threading issue was related to some extra
> > 'From' info in the mail body. I've updated the script to remove it, so
> > we'll see if that fixes the issue in the next version.
>
> OK. I can not fetch the series with b4. So you will have to resend.
>
>
> What about the v6 of "hw/arm/aspeed: AST1700 LTPI support and device
> hookups". Do you plan to resend soon ?
>
> Thanks,
>
> C.
>
Hi Cédric,
Do we need to make any code changes regarding the "i2c-bus-label"?
If not, I will send out the patch series tomorrow.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-03 10:23 ` Kane Chen
@ 2026-02-03 12:56 ` Cédric Le Goater
2026-02-04 7:42 ` Kane Chen
0 siblings, 1 reply; 35+ messages in thread
From: Cédric Le Goater @ 2026-02-03 12:56 UTC (permalink / raw)
To: Kane Chen, Jamin Lin, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
On 2/3/26 11:23, Kane Chen wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Monday, February 2, 2026 6:49 PM
>> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
>> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
>> list:All patches CC here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>
>> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
>> SDRAM remap
>>
>> On 2/2/26 10:46, Kane Chen wrote:
>>>> -----Original Message-----
>>>> From: Cédric Le Goater <clg@kaod.org>
>>>> Sent: Monday, February 2, 2026 5:34 PM
>>>> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
>>>> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
>>>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee
>> <leetroy@gmail.com>;
>>>> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
>>>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
>>>> list:All patches CC here <qemu-devel@nongnu.org>
>>>> Cc: Troy Lee <troy_lee@aspeedtech.com>
>>>> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
>>>> SDRAM remap
>>>>
>>>> Hi,
>>>>
>>>>> Working with our IT team, we've transitioned to a Microsoft mail
>>>>> server to ensure DKIM is correctly included. Could you please
>>>>> confirm if you've received the below patch series?
>>>>>
>>>>>
>>>>
>> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA
>>>> @SE3PR0
>>>>> 6MB8199.apcprd06.prod.outlook.com/
>>>>
>>>> I did. Although, the series is not threaded. Probably due to the way it was
>> sent.
>>>>
>>>> Thanks,
>>>>
>>>> C.
>>>
>>> Hi Cédric,
>>>
>>> Thanks for the confirmation.
>>>
>>> It's possible that the threading issue was related to some extra
>>> 'From' info in the mail body. I've updated the script to remove it, so
>>> we'll see if that fixes the issue in the next version.
>>
>> OK. I can not fetch the series with b4. So you will have to resend.
>>
>>
>> What about the v6 of "hw/arm/aspeed: AST1700 LTPI support and device
>> hookups". Do you plan to resend soon ?
>>
>> Thanks,
>>
>> C.
>>
> Hi Cédric,
>
> Do we need to make any code changes regarding the "i2c-bus-label"?
I don't remember any comments on v5 regarding the bus naming.
Please rebase on top of :
https://lore.kernel.org/qemu-devel/20260203020855.1642884-1-jamin_lin@aspeedtech.com/
Thanks,
C.
> If not, I will send out the patch series tomorrow.
>
> Best Regards,
> Kane
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap
2026-02-03 12:56 ` Cédric Le Goater
@ 2026-02-04 7:42 ` Kane Chen
0 siblings, 0 replies; 35+ messages in thread
From: Kane Chen @ 2026-02-04 7:42 UTC (permalink / raw)
To: Cédric Le Goater, Jamin Lin, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, February 3, 2026 8:57 PM
> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> SDRAM remap
>
> On 2/3/26 11:23, Kane Chen wrote:
> >> -----Original Message-----
> >> From: Cédric Le Goater <clg@kaod.org>
> >> Sent: Monday, February 2, 2026 6:49 PM
> >> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> >> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> >> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee
> <leetroy@gmail.com>;
> >> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> >> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> >> list:All patches CC here <qemu-devel@nongnu.org>
> >> Cc: Troy Lee <troy_lee@aspeedtech.com>
> >> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP
> >> SDRAM remap
> >>
> >> On 2/2/26 10:46, Kane Chen wrote:
> >>>> -----Original Message-----
> >>>> From: Cédric Le Goater <clg@kaod.org>
> >>>> Sent: Monday, February 2, 2026 5:34 PM
> >>>> To: Kane Chen <kane_chen@aspeedtech.com>; Jamin Lin
> >>>> <jamin_lin@aspeedtech.com>; Peter Maydell
> >>>> <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>;
> >>>> Troy Lee
> >> <leetroy@gmail.com>;
> >>>> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> >>>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>;
> open
> >>>> list:All patches CC here <qemu-devel@nongnu.org>
> >>>> Cc: Troy Lee <troy_lee@aspeedtech.com>
> >>>> Subject: Re: [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for
> >>>> SSP SDRAM remap
> >>>>
> >>>> Hi,
> >>>>
> >>>>> Working with our IT team, we've transitioned to a Microsoft mail
> >>>>> server to ensure DKIM is correctly included. Could you please
> >>>>> confirm if you've received the below patch series?
> >>>>>
> >>>>>
> >>>>
> >>
> https://patchew.org/QEMU/SE3PR06MB8199F4B0069F9326034585D6FC9AA
> >>>> @SE3PR0
> >>>>> 6MB8199.apcprd06.prod.outlook.com/
> >>>>
> >>>> I did. Although, the series is not threaded. Probably due to the
> >>>> way it was
> >> sent.
> >>>>
> >>>> Thanks,
> >>>>
> >>>> C.
> >>>
> >>> Hi Cédric,
> >>>
> >>> Thanks for the confirmation.
> >>>
> >>> It's possible that the threading issue was related to some extra
> >>> 'From' info in the mail body. I've updated the script to remove it,
> >>> so we'll see if that fixes the issue in the next version.
> >>
> >> OK. I can not fetch the series with b4. So you will have to resend.
> >>
> >>
> >> What about the v6 of "hw/arm/aspeed: AST1700 LTPI support and device
> >> hookups". Do you plan to resend soon ?
> >>
> >> Thanks,
> >>
> >> C.
> >>
> > Hi Cédric,
> >
> > Do we need to make any code changes regarding the "i2c-bus-label"?
>
> I don't remember any comments on v5 regarding the bus naming.
>
> Please rebase on top of :
>
>
> https://lore.kernel.org/qemu-devel/20260203020855.1642884-1-jamin_lin@
> aspeedtech.com/
>
> Thanks,
>
> C.
>
> > If not, I will send out the patch series tomorrow.
> >
> > Best Regards,
> > Kane
Hi Cédric,
I have submitted the v6 patch series and would appreciate your review.
In this version, I have updated my mail submission script to ensure proper
patch grouping (threading). Based on the Patchew link below, the patches
appear to be correctly grouped as expected:
https://patchew.org/QEMU/20260204064016.3515639-1-kane._5Fchen@aspeedtech.com/
I also want to apologize for the duplicate notifications. I initially did not see
the v6 series appearing in the [qemu-devel] archives, so I attempted a
re-send to my personal address for testing. Unfortunately, my git configuration
automatically CC'd you and Nabih again.
Sorry for the noise and the redundant emails.
Best Regards,
Kane
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2026-02-04 7:42 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-20 9:29 [PATCH v1 00/11] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 01/11] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 02/11] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 03/11] hw/arm/ast27x0: Start TSP " Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-26 9:01 ` Cédric Le Goater
2026-01-27 5:07 ` Jamin Lin
2026-01-27 6:09 ` Jamin Lin
2026-01-27 9:48 ` Jamin Lin
2026-02-02 6:57 ` Kane Chen
2026-02-02 9:33 ` Cédric Le Goater
2026-02-02 9:46 ` Kane Chen
2026-02-02 10:48 ` Cédric Le Goater
2026-02-03 10:23 ` Kane Chen
2026-02-03 12:56 ` Cédric Le Goater
2026-02-04 7:42 ` Kane Chen
2026-01-20 9:29 ` [PATCH v1 05/11] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 07/11] hw/misc/aspeed_scu: Implement TSP " Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 09/11] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 10/11] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
2026-01-20 9:29 ` [PATCH v1 11/11] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin via
2026-01-20 9:29 ` Jamin Lin via qemu development
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