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From: Manali Shukla <manali.shukla@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>
Cc: <mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
	<kvm@vger.kernel.org>, <x86@kernel.org>, <santosh.shukla@amd.com>,
	<nikunj.dadhania@amd.com>, <Naveen.Rao@amd.com>,
	<dapeng1.mi@linux.intel.com>, <manali.shukla@amd.com>
Subject: [PATCH v1 2/9] x86/apic: Add helper to get maximum number of Extended LVT registers
Date: Wed, 4 Feb 2026 07:44:45 +0000	[thread overview]
Message-ID: <20260204074452.55453-3-manali.shukla@amd.com> (raw)
In-Reply-To: <20260204074452.55453-1-manali.shukla@amd.com>

Add lapic_get_max_extlvt() to retrieve the maximum number of Extended
LVT registers supported by the local APIC on AMD processors.  The count
is read from APIC_EFEAT[23:16] (offset 0x400), per AMD APM Volume 2.

Extended LVT registers provide additional interrupt vectors beyond
standard LVT entries, enabling features like Instruction Based Sampling
(IBS). Current AMD processors support four extended LVT entries, but
future processors may support up to 255.

Wrap lapic_get_max_extlvt() with kvm_cpu_get_max_extlvt() for use by
KVM code. Subsequent patches will use this helper to configure the guest's
extended APIC register space.

Signed-off-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apic.h     |  1 +
 arch/x86/include/asm/kvm_host.h | 10 ++++++++++
 arch/x86/kernel/apic/apic.c     | 17 +++++++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index a26e66d66444..d45696563a4e 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -128,6 +128,7 @@ static inline bool apic_is_x2apic_enabled(void)
 extern void enable_IR_x2apic(void);
 
 extern int lapic_get_maxlvt(void);
+extern int lapic_get_max_extlvt(void);
 extern void clear_local_APIC(void);
 extern void disconnect_bsp_APIC(int virt_wire_setup);
 extern void disable_local_APIC(void);
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index ecd4019b84b7..df642723cea6 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -2461,6 +2461,16 @@ static inline int kvm_cpu_get_apicid(int mps_cpu)
 #endif
 }
 
+static inline int kvm_cpu_get_max_extlvt(void)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+	return lapic_get_max_extlvt();
+#else
+	WARN_ON_ONCE(1);
+	return 0;
+#endif
+}
+
 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages);
 
 #define KVM_CLOCK_VALID_FLAGS						\
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index d93f87f29d03..90992ae4852a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -253,6 +253,23 @@ int lapic_get_maxlvt(void)
 	return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
 }
 
+/**
+ * lapic_get_max_extlvt - Get number of extended LVT entries
+ */
+int lapic_get_max_extlvt(void)
+{
+	u32 reg;
+
+	if (!boot_cpu_has(X86_FEATURE_EXTAPIC))
+		return 0;
+
+	reg = apic_read(APIC_EFEAT);
+
+	/* Extract extended LVT count from bits 16-23 */
+	return (reg >> 16) & 0xff;
+}
+EXPORT_SYMBOL_GPL(lapic_get_max_extlvt);
+
 /*
  * Local APIC timer
  */
-- 
2.43.0


  parent reply	other threads:[~2026-02-04  7:45 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-04  7:44 [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-02-04  7:44 ` [PATCH v1 1/9] KVM: x86: Refactor APIC register mask handling to support extended " Manali Shukla
2026-05-14 12:48   ` Naveen N Rao
2026-02-04  7:44 ` Manali Shukla [this message]
2026-05-06 11:22   ` [PATCH v1 2/9] x86/apic: Add helper to get maximum number of Extended LVT registers Borislav Petkov
2026-05-14 12:50   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 3/9] KVM: SVM: Set kvm_caps.has_extapic when CPU supports Extended APIC Manali Shukla
2026-05-14 12:58   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 4/9] KVM: x86: Introduce KVM_CAP_LAPIC2 for 4KB APIC register space support Manali Shukla
2026-05-14 13:08   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 5/9] KVM: x86: Refactor APIC state get/set to accept variable-sized buffers Manali Shukla
2026-05-14 14:20   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 6/9] KVM: Add KVM_GET_LAPIC2 and KVM_SET_LAPIC2 for extended APIC Manali Shukla
2026-03-16 13:00   ` Nikunj A. Dadhania
2026-03-23 11:15     ` Manali Shukla
2026-05-14 14:36       ` Naveen N Rao
2026-05-14 14:41   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 7/9] KVM: x86: Emulate Extended LVT registers for AMD guests Manali Shukla
2026-05-14 14:48   ` Naveen N Rao
2026-02-04  7:44 ` [PATCH v1 8/9] x86/cpufeatures: Add CPUID feature bit for Extended LVT AVIC acceleration Manali Shukla
2026-02-04  7:44 ` [PATCH v1 9/9] KVM: SVM: Add AVIC support for extended LVT MSRs Manali Shukla
2026-05-14 15:10   ` Naveen N Rao
2026-03-10  6:17 ` [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-04-27  4:34   ` Shukla, Manali

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