From: Manali Shukla <manali.shukla@amd.com>
To: <seanjc@google.com>, <pbonzini@redhat.com>
Cc: <mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
<kvm@vger.kernel.org>, <x86@kernel.org>, <santosh.shukla@amd.com>,
<nikunj.dadhania@amd.com>, <Naveen.Rao@amd.com>,
<dapeng1.mi@linux.intel.com>, <manali.shukla@amd.com>
Subject: [PATCH v1 5/9] KVM: x86: Refactor APIC state get/set to accept variable-sized buffers
Date: Wed, 4 Feb 2026 07:44:48 +0000 [thread overview]
Message-ID: <20260204074452.55453-6-manali.shukla@amd.com> (raw)
In-Reply-To: <20260204074452.55453-1-manali.shukla@amd.com>
Refactor kvm_apic_get_state() and kvm_apic_set_state() to accept a void
pointer and explicit size parameter instead of struct kvm_lapic_state.
This removes the hard-coded assumption about 1KB APIC register space and
allows functions to work with both 1KB and 4KB APIC register space.
Existing callers of kvm_apic_get_state() and kvm_apic_set_state() pass
`s->regs` and `sizeof(*s)` to maintain the current behavior with the 1KB
kvm_lapic_state structure. Subsequent patches will add KVM_GET_LAPIC2
and KVM_SET_LAPIC2 IOCTLs that will also use these functions in order to
save/restore 4KB APIC register space.
No functional change intended; existing KVM_GET_LAPIC and KVM_SET_LAPIC
IOCTLs work exactly as before.
Signed-off-by: Manali Shukla <manali.shukla@amd.com>
---
arch/x86/kvm/lapic.c | 32 ++++++++++++++++----------------
arch/x86/kvm/lapic.h | 4 ++--
arch/x86/kvm/x86.c | 4 ++--
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 66819397e073..4ed6abb414e4 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -3151,12 +3151,12 @@ void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector)
EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_apic_ack_interrupt);
static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
- struct kvm_lapic_state *s, bool set)
+ void *regs, bool set)
{
if (apic_x2apic_mode(vcpu->arch.apic)) {
u32 x2apic_id = kvm_x2apic_id(vcpu->arch.apic);
- u32 *id = (u32 *)(s->regs + APIC_ID);
- u32 *ldr = (u32 *)(s->regs + APIC_LDR);
+ u32 *id = (u32 *)(regs + APIC_ID);
+ u32 *ldr = (u32 *)(regs + APIC_LDR);
u64 icr;
if (vcpu->kvm->arch.x2apic_format) {
@@ -3189,12 +3189,12 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
if (!kvm_x86_ops.x2apic_icr_is_split) {
if (set) {
- icr = apic_get_reg(s->regs, APIC_ICR) |
- (u64)apic_get_reg(s->regs, APIC_ICR2) << 32;
- apic_set_reg64(s->regs, APIC_ICR, icr);
+ icr = apic_get_reg(regs, APIC_ICR) |
+ (u64)apic_get_reg(regs, APIC_ICR2) << 32;
+ apic_set_reg64(regs, APIC_ICR, icr);
} else {
- icr = apic_get_reg64(s->regs, APIC_ICR);
- apic_set_reg(s->regs, APIC_ICR2, icr >> 32);
+ icr = apic_get_reg64(regs, APIC_ICR);
+ apic_set_reg(regs, APIC_ICR2, icr >> 32);
}
}
}
@@ -3202,20 +3202,20 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
return 0;
}
-int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
+int kvm_apic_get_state(struct kvm_vcpu *vcpu, void *regs, unsigned int size)
{
- memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
+ memcpy(regs, vcpu->arch.apic->regs, size);
/*
* Get calculated timer current count for remaining timer period (if
* any) and store it in the returned register set.
*/
- apic_set_reg(s->regs, APIC_TMCCT, __apic_read(vcpu->arch.apic, APIC_TMCCT));
+ apic_set_reg(regs, APIC_TMCCT, __apic_read(vcpu->arch.apic, APIC_TMCCT));
- return kvm_apic_state_fixup(vcpu, s, false);
+ return kvm_apic_state_fixup(vcpu, regs, false);
}
-int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
+int kvm_apic_set_state(struct kvm_vcpu *vcpu, void *regs, unsigned int size)
{
struct kvm_lapic *apic = vcpu->arch.apic;
int r;
@@ -3223,14 +3223,14 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
kvm_x86_call(apicv_pre_state_restore)(vcpu);
/* set SPIV separately to get count of SW disabled APICs right */
- apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
+ apic_set_spiv(apic, *((u32 *)(regs + APIC_SPIV)));
- r = kvm_apic_state_fixup(vcpu, s, true);
+ r = kvm_apic_state_fixup(vcpu, regs, true);
if (r) {
kvm_recalculate_apic_map(vcpu->kvm);
return r;
}
- memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
+ memcpy(vcpu->arch.apic->regs, regs, size);
atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
kvm_recalculate_apic_map(vcpu->kvm);
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 152f17903ff0..c6ac40c76f62 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -132,8 +132,8 @@ static inline int kvm_irq_delivery_to_apic(struct kvm *kvm,
void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
-int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
-int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
+int kvm_apic_get_state(struct kvm_vcpu *vcpu, void *regs, unsigned int size);
+int kvm_apic_set_state(struct kvm_vcpu *vcpu, void *regs, unsigned int size);
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 368ee9276366..669c894f1061 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5328,7 +5328,7 @@ static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
kvm_x86_call(sync_pir_to_irr)(vcpu);
- return kvm_apic_get_state(vcpu, s);
+ return kvm_apic_get_state(vcpu, s->regs, sizeof(*s));
}
static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
@@ -5339,7 +5339,7 @@ static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
if (vcpu->arch.apic->guest_apic_protected)
return -EINVAL;
- r = kvm_apic_set_state(vcpu, s);
+ r = kvm_apic_set_state(vcpu, s->regs, sizeof(*s));
if (r)
return r;
update_cr8_intercept(vcpu);
--
2.43.0
next prev parent reply other threads:[~2026-02-04 7:45 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 7:44 [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-02-04 7:44 ` [PATCH v1 1/9] KVM: x86: Refactor APIC register mask handling to support extended " Manali Shukla
2026-05-14 12:48 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 2/9] x86/apic: Add helper to get maximum number of Extended LVT registers Manali Shukla
2026-05-06 11:22 ` Borislav Petkov
2026-05-14 12:50 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 3/9] KVM: SVM: Set kvm_caps.has_extapic when CPU supports Extended APIC Manali Shukla
2026-05-14 12:58 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 4/9] KVM: x86: Introduce KVM_CAP_LAPIC2 for 4KB APIC register space support Manali Shukla
2026-05-14 13:08 ` Naveen N Rao
2026-02-04 7:44 ` Manali Shukla [this message]
2026-05-14 14:20 ` [PATCH v1 5/9] KVM: x86: Refactor APIC state get/set to accept variable-sized buffers Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 6/9] KVM: Add KVM_GET_LAPIC2 and KVM_SET_LAPIC2 for extended APIC Manali Shukla
2026-03-16 13:00 ` Nikunj A. Dadhania
2026-03-23 11:15 ` Manali Shukla
2026-05-14 14:36 ` Naveen N Rao
2026-05-14 14:41 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 7/9] KVM: x86: Emulate Extended LVT registers for AMD guests Manali Shukla
2026-05-14 14:48 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 8/9] x86/cpufeatures: Add CPUID feature bit for Extended LVT AVIC acceleration Manali Shukla
2026-02-04 7:44 ` [PATCH v1 9/9] KVM: SVM: Add AVIC support for extended LVT MSRs Manali Shukla
2026-05-14 15:10 ` Naveen N Rao
2026-03-10 6:17 ` [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-04-27 4:34 ` Shukla, Manali
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