[PATCH v1 01/13] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules

[Changhuang Liang <changhuang.liang@starfivetech.com>]

Add documentation to describe StarFive JHB100 SoC System Controller
Registers.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../soc/starfive/starfive,jhb100-syscon.yaml  | 140 ++++++++++++++++++
 MAINTAINERS                                   |   5 +
 2 files changed, 145 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..c0e1f6f68fa2
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+  - Kevin Xie <kevin.xie@starfivetech.com>
+  - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+  The StarFive JHB100 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules such as PLL and PCIe.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - starfive,jhb100-pcierp-syscon
+              - starfive,jhb100-per0-syscon
+              - starfive,jhb100-per1-syscon
+              - starfive,jhb100-sys0-syscon
+          - const: syscon
+          - const: simple-mfd
+      - items:
+          - enum:
+              - starfive,jhb100-b2h-syscon
+              - starfive,jhb100-gpu-syscon
+              - starfive,jhb100-h2b-syscon
+              - starfive,jhb100-host-syscon
+              - starfive,jhb100-husb-syscon
+              - starfive,jhb100-husbcmn-syscon
+              - starfive,jhb100-husbd-syscon
+              - starfive,jhb100-npu-syscon
+              - starfive,jhb100-pcieep-ecsr-syscon
+              - starfive,jhb100-pcierp-ecsr-syscon
+              - starfive,jhb100-per2-syscon
+              - starfive,jhb100-per3-syscon
+              - starfive,jhb100-strap-syscon
+              - starfive,jhb100-sys1-syscon
+              - starfive,jhb100-sys2-syscon
+              - starfive,jhb100-usb-syscon
+              - starfive,jhb100-vout-syscon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  clock-controller:
+    $ref: /schemas/clock/starfive,jhb100-pll.yaml#
+    type: object
+
+  "#address-cells":
+    const: 2
+
+  "#size-cells":
+    const: 2
+
+  ranges: true
+
+required:
+  - compatible
+  - reg
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - starfive,jhb100-per0-syscon
+              - starfive,jhb100-per1-syscon
+              - starfive,jhb100-sys0-syscon
+    then:
+      required:
+        - clock-controller
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jhb100-sys0-syscon
+    then:
+      required:
+        - "#address-cells"
+        - "#size-cells"
+        - ranges
+      patternProperties:
+        "^chipid@[0-9a-f]+$":
+          $ref: /schemas/hwinfo/starfive,jhb100-socinfo.yaml#
+          type: object
+
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: starfive,jhb100-pcierp-syscon
+    then:
+      required:
+        - "#address-cells"
+        - "#size-cells"
+        - ranges
+      patternProperties:
+        "^reset-controller@[0-9a-f]+$":
+          $ref: /schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        syscon@10240000 {
+            compatible = "starfive,jhb100-b2h-syscon", "syscon";
+            reg = <0x0 0x10240000 0x0 0x1000>;
+        };
+
+        syscon@11719000 {
+            compatible = "starfive,jhb100-pcierp-syscon", "syscon",
+                         "simple-mfd";
+            reg = <0x0 0x11719000 0x0 0x1000>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges = <0x0 0x0 0x0 0x11719000 0x0 0x1000>;
+
+            reset-controller@14c {
+                compatible = "starfive,jhb100-reset-pcierp";
+                reg = <0x0 0x14c 0x0 0x4>;
+                #reset-cells = <1>;
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 4ddf8ba2e60d..eb5f6a383146 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25325,6 +25325,11 @@ S:	Maintained
 F:	drivers/reset/starfive/reset-starfive-jhb1*
 F:	include/dt-bindings/reset/starfive,jhb1*.h
 
+STARFIVE JHB100 SYSCON
+M:	Changhuang Liang <changhuang.liang@starfivetech.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
-- 
2.25.1