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From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Alexey Charkov <alchark@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Keguang Zhang <keguang.zhang@gmail.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	Ley Foon Tan <leyfoon.tan@starfivetech.com>,
	Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator
Date: Thu,  2 Apr 2026 22:49:40 -0700	[thread overview]
Message-ID: <20260403054945.467700-9-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>

Add bindings for thr reset generator which locates in pcierp syscon.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../reset/starfive,jhb100-reset-pcierp.yaml   | 38 +++++++++++++++++++
 .../dt-bindings/reset/starfive,jhb100-crg.h   |  3 ++
 2 files changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml

diff --git a/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
new file mode 100644
index 000000000000..fc6b0d1e64f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC PCIe root port Reset Controller
+
+maintainers:
+  - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jhb100-reset-pcierp
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@14c {
+        compatible = "starfive,jhb100-reset-pcierp";
+        reg = <0x14c 0x4>;
+        #reset-cells = <1>;
+    };
+
+...
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 4b15e348e92f..49326b7f486f 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -190,4 +190,7 @@
 #define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS			5
 #define JHB100_PER3RST_IOMUX_PRESETN					6
 
+/* PCIERP SYSCON resets */
+#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT				0
+
 #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Alexey Charkov <alchark@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Keguang Zhang <keguang.zhang@gmail.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	Ley Foon Tan <leyfoon.tan@starfivetech.com>,
	Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator
Date: Thu,  2 Apr 2026 22:49:40 -0700	[thread overview]
Message-ID: <20260403054945.467700-9-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260403054945.467700-1-changhuang.liang@starfivetech.com>

Add bindings for thr reset generator which locates in pcierp syscon.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../reset/starfive,jhb100-reset-pcierp.yaml   | 38 +++++++++++++++++++
 .../dt-bindings/reset/starfive,jhb100-crg.h   |  3 ++
 2 files changed, 41 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml

diff --git a/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
new file mode 100644
index 000000000000..fc6b0d1e64f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jhb100-reset-pcierp.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jhb100-reset-pcierp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC PCIe root port Reset Controller
+
+maintainers:
+  - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jhb100-reset-pcierp
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@14c {
+        compatible = "starfive,jhb100-reset-pcierp";
+        reg = <0x14c 0x4>;
+        #reset-cells = <1>;
+    };
+
+...
diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
index 4b15e348e92f..49326b7f486f 100644
--- a/include/dt-bindings/reset/starfive,jhb100-crg.h
+++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
@@ -190,4 +190,7 @@
 #define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS			5
 #define JHB100_PER3RST_IOMUX_PRESETN					6
 
+/* PCIERP SYSCON resets */
+#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT				0
+
 #endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */
-- 
2.25.1


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  parent reply	other threads:[~2026-04-03  5:50 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-03  5:49 [PATCH v1 00/13] Add StarFive JHB100 syscon modules Changhuang Liang
2026-04-03  5:49 ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 01/13] dt-bindings: soc: starfive: " Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-05  7:17   ` Krzysztof Kozlowski
2026-04-05  7:17     ` Krzysztof Kozlowski
2026-04-07  7:34     ` Changhuang Liang
2026-04-07  7:34       ` Changhuang Liang
2026-04-07  7:37       ` Krzysztof Kozlowski
2026-04-07  7:37         ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 02/13] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-05  7:18   ` Krzysztof Kozlowski
2026-04-05  7:18     ` Krzysztof Kozlowski
2026-04-07  6:56     ` Changhuang Liang
2026-04-07  6:56       ` Changhuang Liang
2026-04-07  7:02       ` Krzysztof Kozlowski
2026-04-07  7:02         ` Krzysztof Kozlowski
2026-04-08  5:17         ` Changhuang Liang
2026-04-08  5:17           ` Changhuang Liang
2026-04-08  6:29           ` Krzysztof Kozlowski
2026-04-08  6:29             ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 03/13] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03 16:10   ` Brian Masney
2026-04-03 16:10     ` Brian Masney
2026-04-07  1:17     ` Changhuang Liang
2026-04-07  1:17       ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 04/13] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 05/13] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 06/13] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 07/13] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` Changhuang Liang [this message]
2026-04-03  5:49   ` [PATCH v1 08/13] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 09/13] reset: starfive: Introduce assert_polarity Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 10/13] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 11/13] dt-bindings: hwinfo: Add starfive,jhb100-socinfo Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-05  7:19   ` Krzysztof Kozlowski
2026-04-05  7:19     ` Krzysztof Kozlowski
2026-04-07  6:49     ` Changhuang Liang
2026-04-07  6:49       ` Changhuang Liang
2026-04-07  7:06       ` Krzysztof Kozlowski
2026-04-07  7:06         ` Krzysztof Kozlowski
2026-04-03  5:49 ` [PATCH v1 12/13] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-07 15:43   ` Conor Dooley
2026-04-07 15:43     ` Conor Dooley
2026-04-07 15:47   ` Conor Dooley
2026-04-07 15:47     ` Conor Dooley
2026-04-08  6:26     ` Changhuang Liang
2026-04-08  6:26       ` Changhuang Liang
2026-04-03  5:49 ` [PATCH v1 13/13] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-04-03  5:49   ` Changhuang Liang
2026-04-05  7:18 ` [PATCH v1 00/13] Add StarFive JHB100 syscon modules Krzysztof Kozlowski
2026-04-05  7:18   ` Krzysztof Kozlowski

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