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From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Kane Chen" <kane_chen@aspeedtech.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Hanna Reitz" <hreitz@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:Block layer core" <qemu-block@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v4 12/21] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP
Date: Fri, 17 Apr 2026 03:28:54 +0000	[thread overview]
Message-ID: <20260417032837.2664122-13-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260417032837.2664122-1-jamin_lin@aspeedtech.com>

The AST2700 SSP/TSP firmware accesses Privilege Controller MMIO regions that
are not yet implemented in QEMU.

This change adds unimplemented MMIO devices for the Privilege Controller
blocks and maps them to their corresponding physical addresses in the SSP/TSP
address space. These stub devices allow QEMU to safely handle firmware
accesses and prevent spurious exceptions, while accurately reflecting
the hardware memory map.

No functional changes.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/arm/aspeed_coprocessor.h |  1 +
 include/hw/arm/aspeed_soc.h         |  2 ++
 hw/arm/aspeed_ast27x0-ssp.c         | 12 ++++++++++++
 hw/arm/aspeed_ast27x0-tsp.c         | 12 ++++++++++++
 4 files changed, 27 insertions(+)

diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 2460a11401..084040bbed 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -46,6 +46,7 @@ struct Aspeed27x0CoprocessorState {
     AspeedINTCState intc[2];
     UnimplementedDeviceState ipc[2];
     UnimplementedDeviceState scuio;
+    UnimplementedDeviceState pric[2];
 
     ARMv7MState armv7m;
 
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index adf2f2898a..d39e4f7553 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -297,6 +297,8 @@ enum {
     ASPEED_DEV_IOEXP1_INTCIO,
     ASPEED_DEV_IOEXP0_I3C,
     ASPEED_DEV_IOEXP1_I3C,
+    ASPEED_DEV_PRIC0,
+    ASPEED_DEV_PRIC1,
 };
 
 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index bfd6fe4485..467fdea9db 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -22,11 +22,13 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
     [ASPEED_DEV_SDRAM]     =  0x00000000,
     [ASPEED_DEV_SRAM]      =  0x70000000,
     [ASPEED_DEV_INTC]      =  0x72100000,
+    [ASPEED_DEV_PRIC0]     =  0x72140000,
     [ASPEED_DEV_SCU]       =  0x72C02000,
     [ASPEED_DEV_TIMER1]    =  0x72C10000,
     [ASPEED_DEV_UART4]     =  0x72C1A000,
     [ASPEED_DEV_IPC0]      =  0x72C1C000,
     [ASPEED_DEV_FMC]       =  0x74000000,
+    [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
@@ -142,6 +144,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "scuio", &a->scuio,
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric0", &a->pric[0],
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric1", &a->pric[1],
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
@@ -276,6 +282,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
                                   "aspeed.scuio",
                                   sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
+                                  "aspeed.pric0",
+                                  sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
+                                  "aspeed.pric1",
+                                  sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
 }
 
 static const Property aspeed_27x0_coprocessor_properties[] = {
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 166dcb14ed..3a90bbec51 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -22,11 +22,13 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
     [ASPEED_DEV_SDRAM]     =  0x00000000,
     [ASPEED_DEV_SRAM]      =  0x70000000,
     [ASPEED_DEV_INTC]      =  0x72100000,
+    [ASPEED_DEV_PRIC0]     =  0x72140000,
     [ASPEED_DEV_SCU]       =  0x72C02000,
     [ASPEED_DEV_TIMER1]    =  0x72C10000,
     [ASPEED_DEV_UART4]     =  0x72C1A000,
     [ASPEED_DEV_IPC0]      =  0x72C1C000,
     [ASPEED_DEV_FMC]       =  0x74000000,
+    [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
@@ -142,6 +144,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "scuio", &a->scuio,
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric0", &a->pric[0],
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric1", &a->pric[1],
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
@@ -273,6 +279,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
                                   "aspeed.scuio",
                                   sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
+                                  "aspeed.pric0",
+                                  sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
+                                  "aspeed.pric1",
+                                  sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
 }
 
 static const Property aspeed_27x0_coprocessor_properties[] = {
-- 
2.43.0


  parent reply	other threads:[~2026-04-17  3:33 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-17  3:28 [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-04-17  3:28 ` [PATCH v4 01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass and separate from generic SCU Jamin Lin
2026-06-01 17:05   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 02/21] hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO Jamin Lin
2026-04-17  3:28 ` [PATCH v4 03/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
2026-04-17  3:28 ` [PATCH v4 04/21] hw/arm/ast27x0: Start TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 05/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
2026-06-01 17:07   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 06/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 07/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
2026-04-17  3:28 ` [PATCH v4 08/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 09/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
2026-06-01 17:28   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 10/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 11/21] hw/arm/ast27x0: Share FMC controller with SSP and TSP Jamin Lin
2026-06-01 17:18   ` Cédric Le Goater
2026-04-17  3:28 ` Jamin Lin [this message]
2026-06-01 17:19   ` [PATCH v4 12/21] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 13/21] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller " Jamin Lin
2026-06-01 17:19   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 14/21] hw/block/m25p80: Implement volatile status register write enable for Winbond Jamin Lin
2026-06-01 17:31   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 15/21] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Jamin Lin
2026-04-17  3:28 ` [PATCH v4 16/21] hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700 SCU/SCUIO Jamin Lin
2026-06-01 17:20   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 17/21] hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers Jamin Lin
2026-06-01 17:21   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP Jamin Lin
2026-06-01 17:23   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 19/21] hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings Jamin Lin
2026-06-01 17:23   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 20/21] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
2026-04-17  3:29 ` [PATCH v4 21/21] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
2026-05-21  6:42 ` [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Cédric Le Goater
2026-05-21  6:47   ` Jamin Lin

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