From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Kane Chen" <kane_chen@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"Kevin Wolf" <kwolf@redhat.com>,
"Hanna Reitz" <hreitz@redhat.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:Block layer core" <qemu-block@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP
Date: Fri, 17 Apr 2026 03:29:02 +0000 [thread overview]
Message-ID: <20260417032837.2664122-19-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260417032837.2664122-1-jamin_lin@aspeedtech.com>
AST2700 has a single SCUIO hardware block, memory-mapped at
0x14C02000–0x14C03FFF from the perspective of the main CA35 processor (PSP).
The SSP and TSP coprocessors access this same SCUIO block at different
addresses: 0x74C02000–0x74C03FFF.
Previously, each subsystem (PSP, SSP, and TSP) instantiated its own SCUIO
device, resulting in three independent SCUIO instances in the QEMU model.
In real hardware, however, only a single SCUIO exists and is shared among
all processors.
This commit reworks the SCUIO model to correctly reflect the hardware
behavior by allowing SSP and TSP to reference the PSP’s SCUIO instance.
The following changes are introduced:
- Add a scuio property to Aspeed27x0CoprocessorState for linking the
coprocessor to the PSP’s SCUIO instance.
- Replace per-coprocessor SCUIO instantiation with a shared SCUIO link.
- Add "MemoryRegion scuio_alias" to model address remapping for SSP and TSP.
- Create SCUIO alias regions in both SSP and TSP coprocessors and map
them at 0x74C02000 to mirror the PSP’s SCUIO registers.
- Ensure the SCUIO device in PSP is realized before SSP/TSP alias setup.
With this change, PSP, SSP, and TSP now share a consistent SCUIO state,
matching the single-SCUIO hardware design of AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_coprocessor.h | 4 ++--
hw/arm/aspeed_ast27x0-fc.c | 4 ++++
hw/arm/aspeed_ast27x0-ssp.c | 14 +++++++++-----
hw/arm/aspeed_ast27x0-tsp.c | 14 +++++++++-----
4 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 7750569eed..23c3b97f06 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -22,7 +22,6 @@ struct AspeedCoprocessorState {
MemoryRegion uart_alias;
Clock *sysclk;
- AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
SerialMM *uart;
int uart_dev;
@@ -45,15 +44,16 @@ struct Aspeed27x0CoprocessorState {
AspeedCoprocessorState parent;
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
UnimplementedDeviceState pric[2];
UnimplementedDeviceState otp;
ARMv7MState armv7m;
MemoryRegion scu_alias;
+ MemoryRegion scuio_alias;
MemoryRegion fmc_alias;
Aspeed2700SCUState *scu;
+ AspeedSCUState *scuio;
AspeedSMCState *fmc;
};
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 56dd86e2c2..d1ff6fbd4d 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -161,6 +161,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp), "scuio",
+ OBJECT(&psp->scuio), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "fmc",
OBJECT(&psp->fmc), &error_abort);
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
@@ -195,6 +197,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp), "scuio",
+ OBJECT(&psp->scuio), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "fmc",
OBJECT(&psp->fmc), &error_abort);
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 78bd6f342c..6c8945ce6c 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -143,8 +143,6 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc1", &a->ipc[1],
TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "scuio", &a->scuio,
- TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric0", &a->pric[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric1", &a->pric[1],
@@ -215,6 +213,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
memory_region_size(&a->scu->dram_remap_alias[1]),
&a->scu->dram_remap_alias[0]);
+ /* SCUIO */
+ memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
+ &a->scuio->iomem, 0,
+ memory_region_size(&a->scuio->iomem));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
+ &a->scuio_alias);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
@@ -282,9 +287,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
- "aspeed.scuio",
- sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
"aspeed.pric0",
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
@@ -299,6 +301,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
+ DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
+ TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
};
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index d6448d82f5..cab7f47ac8 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -143,8 +143,6 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "ipc1", &a->ipc[1],
TYPE_UNIMPLEMENTED_DEVICE);
- object_initialize_child(obj, "scuio", &a->scuio,
- TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric0", &a->pric[0],
TYPE_UNIMPLEMENTED_DEVICE);
object_initialize_child(obj, "pric1", &a->pric[1],
@@ -212,6 +210,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
/* SDRAM remap alias used by PSP to access TSP SDRAM */
memory_region_add_subregion(&s->sdram, 0, &a->scu->dram_remap_alias[2]);
+ /* SCUIO */
+ memory_region_init_alias(&a->scuio_alias, OBJECT(a), "scuio.alias",
+ &a->scuio->iomem, 0,
+ memory_region_size(&a->scuio->iomem));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],
+ &a->scuio_alias);
+
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
@@ -279,9 +284,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->ipc[1]),
"aspeed.ipc1",
sc->memmap[ASPEED_DEV_IPC1], 0x1000);
- aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
- "aspeed.scuio",
- sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
"aspeed.pric0",
sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
@@ -296,6 +298,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
+ DEFINE_PROP_LINK("scuio", Aspeed27x0CoprocessorState, scuio,
+ TYPE_ASPEED_SCU, AspeedSCUState *),
DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
AspeedSMCState *),
};
--
2.43.0
next prev parent reply other threads:[~2026-04-17 3:32 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 3:28 [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-04-17 3:28 ` [PATCH v4 01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass and separate from generic SCU Jamin Lin
2026-06-01 17:05 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 02/21] hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO Jamin Lin
2026-04-17 3:28 ` [PATCH v4 03/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
2026-04-17 3:28 ` [PATCH v4 04/21] hw/arm/ast27x0: Start TSP " Jamin Lin
2026-04-17 3:28 ` [PATCH v4 05/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
2026-06-01 17:07 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 06/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
2026-04-17 3:28 ` [PATCH v4 07/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
2026-04-17 3:28 ` [PATCH v4 08/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
2026-04-17 3:28 ` [PATCH v4 09/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
2026-06-01 17:28 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 10/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
2026-04-17 3:28 ` [PATCH v4 11/21] hw/arm/ast27x0: Share FMC controller with SSP and TSP Jamin Lin
2026-06-01 17:18 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 12/21] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP Jamin Lin
2026-06-01 17:19 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 13/21] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller " Jamin Lin
2026-06-01 17:19 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 14/21] hw/block/m25p80: Implement volatile status register write enable for Winbond Jamin Lin
2026-06-01 17:31 ` Cédric Le Goater
2026-04-17 3:28 ` [PATCH v4 15/21] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Jamin Lin
2026-04-17 3:28 ` [PATCH v4 16/21] hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700 SCU/SCUIO Jamin Lin
2026-06-01 17:20 ` Cédric Le Goater
2026-04-17 3:29 ` [PATCH v4 17/21] hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers Jamin Lin
2026-06-01 17:21 ` Cédric Le Goater
2026-04-17 3:29 ` Jamin Lin [this message]
2026-06-01 17:23 ` [PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP Cédric Le Goater
2026-04-17 3:29 ` [PATCH v4 19/21] hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings Jamin Lin
2026-06-01 17:23 ` Cédric Le Goater
2026-04-17 3:29 ` [PATCH v4 20/21] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
2026-04-17 3:29 ` [PATCH v4 21/21] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
2026-05-21 6:42 ` [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Cédric Le Goater
2026-05-21 6:47 ` Jamin Lin
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