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From: Jamin Lin <jamin_lin@aspeedtech.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Kane Chen" <kane_chen@aspeedtech.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Hanna Reitz" <hreitz@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:Block layer core" <qemu-block@nongnu.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>
Subject: [PATCH v4 14/21] hw/block/m25p80: Implement volatile status register write enable for Winbond
Date: Fri, 17 Apr 2026 03:28:57 +0000	[thread overview]
Message-ID: <20260417032837.2664122-15-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20260417032837.2664122-1-jamin_lin@aspeedtech.com>

Winbond SPI NOR flashes require the Volatile Status Register Write Enable
(VSR WREN, opcode 0x50) command to be issued before updating volatile
status register bits, such as those accessed via the WRSR2 command.

Currently, WRSR2 handling only checks the standard write enable latch,
which does not fully model Winbond hardware behavior.

Add support for the volatile write enable mechanism by introducing a
separate volatile_write_enable flag. For Winbond devices, WRSR2 writes
that update volatile status register bits are gated by the VSR WREN
command. If the volatile write enable latch is not set, such writes are
rejected.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/block/m25p80.c | 36 ++++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b8a2543c0b..5bb8b8efa9 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -438,6 +438,11 @@ typedef enum {
      */
     WRSR2 = 0x31,
 
+    /*
+     * Winbond: 0x50 - Write Enable for Volatile Status Register
+     */
+    VSR_WREN = 0x50,
+
     RNVCR = 0xB5,
     WNVCR = 0xB1,
 
@@ -510,6 +515,7 @@ struct Flash {
     uint8_t spansion_cr4v;
     bool wp_level;
     bool write_enable;
+    bool volatile_write_enable;
     bool four_bytes_address_mode;
     bool reset_enable;
     bool quad_enable;
@@ -897,6 +903,7 @@ static void reset_memory(Flash *s)
     s->pos = 0;
     s->state = STATE_IDLE;
     s->write_enable = false;
+    s->volatile_write_enable = false;
     s->reset_enable = false;
     s->quad_enable = false;
     s->aai_enable = false;
@@ -1305,8 +1312,7 @@ static void decode_new_cmd(Flash *s, uint32_t value)
          * combinations of the two states are called "software protected mode"
          * (SPM), and status register writes are permitted.
          */
-        if ((s->wp_level == 0 && s->status_register_write_disabled)
-            || !s->write_enable) {
+        if (s->wp_level == 0 && s->status_register_write_disabled) {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "M25P80: Status register 2 write is disabled!\n");
             break;
@@ -1314,6 +1320,17 @@ static void decode_new_cmd(Flash *s, uint32_t value)
 
         switch (get_man(s)) {
         case MAN_WINBOND:
+            /*
+             * Winbond requires VSR WREN (0x50) prior to updating volatile
+             * status register bits. VSR WREN does not set WEL.
+             *
+             * Accept either standard WEL (0x06) or VSR WREN (0x50).
+             */
+            if (!s->write_enable && !s->volatile_write_enable) {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "M25P80: Status register 2 write is disabled!\n");
+                break;
+            }
             s->needed_bytes = 1;
             s->state = STATE_COLLECTING_DATA;
             s->pos = 0;
@@ -1332,6 +1349,16 @@ static void decode_new_cmd(Flash *s, uint32_t value)
         s->write_enable = true;
         break;
 
+    case VSR_WREN:
+        switch (get_man(s)) {
+        case MAN_WINBOND:
+            s->volatile_write_enable = true;
+            break;
+        default:
+            break;
+        }
+        break;
+
     case RDSR:
         s->data[0] = (!!s->write_enable) << 1;
         s->data[0] |= (!!s->status_register_write_disabled) << 7;
@@ -1824,8 +1851,8 @@ static const VMStateDescription vmstate_m25p80_block_protect = {
 
 static const VMStateDescription vmstate_m25p80 = {
     .name = "m25p80",
-    .version_id = 0,
-    .minimum_version_id = 0,
+    .version_id = 1,
+    .minimum_version_id = 1,
     .pre_save = m25p80_pre_save,
     .pre_load = m25p80_pre_load,
     .fields = (const VMStateField[]) {
@@ -1837,6 +1864,7 @@ static const VMStateDescription vmstate_m25p80 = {
         VMSTATE_UINT8(cmd_in_progress, Flash),
         VMSTATE_UINT32(cur_addr, Flash),
         VMSTATE_BOOL(write_enable, Flash),
+        VMSTATE_BOOL(volatile_write_enable, Flash),
         VMSTATE_BOOL(reset_enable, Flash),
         VMSTATE_UINT8(ear, Flash),
         VMSTATE_BOOL(four_bytes_address_mode, Flash),
-- 
2.43.0


  parent reply	other threads:[~2026-04-17  3:32 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-17  3:28 [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Jamin Lin
2026-04-17  3:28 ` [PATCH v4 01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass and separate from generic SCU Jamin Lin
2026-06-01 17:05   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 02/21] hw/misc/aspeed_scu: Add separate reset handler for AST2700 SCUIO Jamin Lin
2026-04-17  3:28 ` [PATCH v4 03/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin
2026-04-17  3:28 ` [PATCH v4 04/21] hw/arm/ast27x0: Start TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 05/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Jamin Lin
2026-06-01 17:07   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 06/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 07/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin
2026-04-17  3:28 ` [PATCH v4 08/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 09/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin
2026-06-01 17:28   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 10/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin
2026-04-17  3:28 ` [PATCH v4 11/21] hw/arm/ast27x0: Share FMC controller with SSP and TSP Jamin Lin
2026-06-01 17:18   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 12/21] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP Jamin Lin
2026-06-01 17:19   ` Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 13/21] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller " Jamin Lin
2026-06-01 17:19   ` Cédric Le Goater
2026-04-17  3:28 ` Jamin Lin [this message]
2026-06-01 17:31   ` [PATCH v4 14/21] hw/block/m25p80: Implement volatile status register write enable for Winbond Cédric Le Goater
2026-04-17  3:28 ` [PATCH v4 15/21] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Jamin Lin
2026-04-17  3:28 ` [PATCH v4 16/21] hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700 SCU/SCUIO Jamin Lin
2026-06-01 17:20   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 17/21] hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers Jamin Lin
2026-06-01 17:21   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP, and TSP Jamin Lin
2026-06-01 17:23   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 19/21] hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings Jamin Lin
2026-06-01 17:23   ` Cédric Le Goater
2026-04-17  3:29 ` [PATCH v4 20/21] tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP and load binaries from DRAM Jamin Lin
2026-04-17  3:29 ` [PATCH v4 21/21] docs: Add support vbootrom and update Manual boot for ast2700fc Jamin Lin
2026-05-21  6:42 ` [PATCH v4 00/21] Add SSP/TSP power control and DRAM remap support for AST2700 Cédric Le Goater
2026-05-21  6:47   ` Jamin Lin

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