All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Mohamed Mediouni <mohamed@unpredictable.fr>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Phil Dennis-Jordan <phil@philjordan.eu>,
	Roman Bolshakov <rbolshakov@ddn.com>,
	Pierrick Bouvier <pierrick.bouvier@linaro.org>,
	Pedro Barbuda <pbarbuda@microsoft.com>,
	Wei Liu <wei.liu@kernel.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v2 22/38] whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip
Date: Mon, 20 Apr 2026 12:42:32 +0200	[thread overview]
Message-ID: <20260420104248.86702-23-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260420104248.86702-1-mohamed@unpredictable.fr>

Add support for an oddball HV_X64_MSR_GUEST_IDLE not-quite-an-HLT
that wakes the vCPU even if EFLAGS.IF is set.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
 target/i386/whpx/whpx-all.c | 46 ++++++++++++++++++++++++++++++++++---
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index 3af5f936d4..4dc4030d87 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -52,6 +52,7 @@
 /* for kernel-irqchip=off */
 #define HV_X64_MSR_APIC_FREQUENCY       0x40000023
 #define HV_X64_MSR_VP_ASSIST_PAGE       0x40000073
+#define HV_X64_MSR_GUEST_IDLE           0x400000f0
 
 static bool is_modern_os = true;
 
@@ -1543,13 +1544,16 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid)
     }
 }
 
-static int whpx_handle_halt(CPUState *cpu)
+static int whpx_handle_halt_generic(CPUState *cpu)
 {
+    X86CPU *x86_cpu = X86_CPU(cpu);
+    CPUX86State *env = &x86_cpu->env;
+
     int ret = 0;
 
     bql_lock();
     if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) &&
-          (cpu_env(cpu)->eflags & IF_MASK)) &&
+          ((cpu_env(cpu)->eflags & IF_MASK) || env->hflags2 & HF2_HYPERV_HLT_MASK)) &&
         !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) {
         cpu->exception_index = EXCP_HLT;
         cpu->halted = true;
@@ -1560,6 +1564,27 @@ static int whpx_handle_halt(CPUState *cpu)
     return ret;
 }
 
+static int whpx_handle_halt(CPUState *cpu)
+{
+    int ret = 0;
+
+    ret = whpx_handle_halt_generic(cpu);
+
+    return ret;
+}
+
+static int whpx_handle_hyperv_guestidle(CPUState *cpu)
+{
+    X86CPU *x86_cpu = X86_CPU(cpu);
+    CPUX86State *env = &x86_cpu->env;
+    int ret = 0;
+
+    env->hflags2 |= HF2_HYPERV_HLT_MASK;
+    ret = whpx_handle_halt_generic(cpu);
+
+    return ret;
+}
+
 static void whpx_vcpu_kick_out_of_hlt(CPUState *cpu) 
 {
     WHV_REGISTER_VALUE reg;
@@ -1763,9 +1788,10 @@ static void whpx_vcpu_process_async_events(CPUState *cpu)
     }
 
     if ((cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) &&
-         (env->eflags & IF_MASK)) ||
+         ((env->eflags & IF_MASK) || env->hflags2 & HF2_HYPERV_HLT_MASK)) ||
         cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) {
         cpu->halted = false;
+        env->hflags2 &= ~HF2_HYPERV_HLT_MASK;
     }
 
     if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) {
@@ -2035,6 +2061,20 @@ int whpx_vcpu_run(CPUState *cpu)
                 }
             }
 
+            /*
+             * Windows and Linux both use this MSR.
+             * Windows 11 25H2 uses it even when not advertised.
+             */
+            if (vcpu->exit_ctx.MsrAccess.MsrNumber == HV_X64_MSR_GUEST_IDLE
+                && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite
+                && !whpx_irqchip_in_kernel()
+                && whpx->hyperv_enlightenments_enabled) {
+                is_known_msr = 1;
+                whpx_bump_rip(cpu, &vcpu->exit_ctx);
+                ret = whpx_handle_hyperv_guestidle(cpu);
+                break;
+            }
+
             /*
              * Linux tries to use it anyway even when not exposed. 
              * Ignore the write as the VP assist page is not used.
-- 
2.50.1 (Apple Git-155)



  parent reply	other threads:[~2026-04-20 10:48 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-04-20 10:42 [PATCH v2 00/38] WHPX x86 updates for QEMU 11.1 Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 01/38] target/i386: emulate: include name of unhandled instruction Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 02/38] whpx: i386: x2apic emulation Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 03/38] whpx: i386: wire up feature probing Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 04/38] whpx: i386: disable TbFlushHypercalls for emulated LAPIC Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 05/38] whpx: i386: enable x2apic by default for user-mode LAPIC Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 06/38] whpx: i386: reintroduce enlightenments for Windows 10 Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 07/38] whpx: i386: introduce proper cpuid support Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 08/38] whpx: i386: kernel-irqchip=off fixes Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 09/38] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 10/38] whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 11/38] whpx: i386: IO port fast path cleanup Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 12/38] whpx: i386: disable enlightenments and LAPIC for isapc Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 13/38] whpx: i386: interrupt priority support Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 14/38] hw/intc: apic: disallow APIC reads when disabled Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 15/38] whpx: i386: fix CPUID[1:EDX].APIC reporting Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 16/38] whpx: i386: set apicbase value only on success Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 17/38] whpx: i386: unknown MSR configurability Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 18/38] whpx: i386: enable GuestIdleReg enlightenment Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 19/38] whpx: i386: tighten APIC base validity check Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 20/38] whpx: i386: ignore vpassist when kernel-irqchip=off Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 21/38] target: i386: HLT type that ignores EFLAGS.IF Mohamed Mediouni
2026-04-20 10:42 ` Mohamed Mediouni [this message]
2026-04-20 10:42 ` [PATCH v2 23/38] whpx: i386: one more CPUID Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 24/38] whpx: i386: some x2APIC awareness Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 25/38] whpx: i386: set WHvX64RegisterInitialApicId Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 26/38] whpx: i386: Pause VM on fatal exception to be able to inspect state Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 27/38] target/i386: emulate: use exception_payload for fault address Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 28/38] whpx: i386: CPU features support for Windows 10 Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 29/38] target/i386: make xsave_buf present unconditionally Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 30/38] target/i386: add de/compaction to xsave_helper Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 31/38] whpx: xsave support Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 32/38] whpx: i386: set APIC ID only when APIC present Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 33/38] whpx: i386: update migration blocker message Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 34/38] whpx: i386: don't increment eip on MSR access raising GPF Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 35/38] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling Mohamed Mediouni
2026-04-20 11:27   ` Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 36/38] whpx: i386: add feature to intercept #GP MSR accesses Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 37/38] whpx: i386: intercept CPUID 0xD too Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 38/38] whpx: i386: documentation update Mohamed Mediouni

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260420104248.86702-23-mohamed@unpredictable.fr \
    --to=mohamed@unpredictable.fr \
    --cc=mst@redhat.com \
    --cc=pbarbuda@microsoft.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=phil@philjordan.eu \
    --cc=pierrick.bouvier@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=rbolshakov@ddn.com \
    --cc=wei.liu@kernel.org \
    --cc=zhao1.liu@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.