From: Mohamed Mediouni <mohamed@unpredictable.fr>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Mohamed Mediouni <mohamed@unpredictable.fr>,
Paolo Bonzini <pbonzini@redhat.com>,
Phil Dennis-Jordan <phil@philjordan.eu>,
Roman Bolshakov <rbolshakov@ddn.com>,
Pierrick Bouvier <pierrick.bouvier@linaro.org>,
Pedro Barbuda <pbarbuda@microsoft.com>,
Wei Liu <wei.liu@kernel.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
Peter Maydell <peter.maydell@linaro.org>,
Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v2 07/38] whpx: i386: introduce proper cpuid support
Date: Mon, 20 Apr 2026 12:42:17 +0200 [thread overview]
Message-ID: <20260420104248.86702-8-mohamed@unpredictable.fr> (raw)
In-Reply-To: <20260420104248.86702-1-mohamed@unpredictable.fr>
Unlike the implementation in QEMU 10.2, this one works.
It's not optimal though as it doesn't use the Hyper-V support for this.
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
---
target/i386/whpx/whpx-all.c | 123 ++++++++++++++++++++++++++++++++++--
1 file changed, 119 insertions(+), 4 deletions(-)
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index c2a78312f8..53b59a98b9 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -2071,6 +2071,7 @@ int whpx_vcpu_run(CPUState *cpu)
WHV_REGISTER_NAME reg_names[5];
UINT32 reg_count = 5;
X86CPU *x86_cpu = X86_CPU(cpu);
+ X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
CPUX86State *env = &x86_cpu->env;
reg_names[0] = WHvX64RegisterRip;
@@ -2083,7 +2084,15 @@ int whpx_vcpu_run(CPUState *cpu)
vcpu->exit_ctx.VpContext.Rip +
vcpu->exit_ctx.VpContext.InstructionLength;
- if (whpx_is_legacy_os()) {
+ /*
+ * On Windows 10 we can't query features from
+ * the Hyper-V interface.
+ *
+ * On Windows 11, if using xcc->max_features
+ * just pass through what the hypervisor
+ * provides without any QEMU filtering.
+ */
+ if (whpx_is_legacy_os() || xcc->max_features) {
reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
@@ -2135,6 +2144,60 @@ int whpx_vcpu_run(CPUState *cpu)
}
break;
}
+ } else {
+ switch (vcpu->exit_ctx.CpuidAccess.Rax) {
+ case 0x40000000:
+ case 0x40000001:
+ case 0x40000010:
+ reg_values[1].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRax;
+ reg_values[2].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRcx;
+ reg_values[3].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRdx;
+ reg_values[4].Reg64 = vcpu->exit_ctx.CpuidAccess.DefaultResultRbx;
+ break;
+ }
+ }
+
+ if (vcpu->exit_ctx.CpuidAccess.Rax == 0x1) {
+ if (cpu_has_x2apic_feature(env)) {
+ reg_values[2].Reg64 |= CPUID_EXT_X2APIC;
+ } else {
+ reg_values[2].Reg32 &= ~CPUID_EXT_X2APIC;
+ }
+ }
+
+ /* Dynamic depending on XCR0 and XSS, so query DefaultResult */
+ if (vcpu->exit_ctx.CpuidAccess.Rax == 0x07
+ && vcpu->exit_ctx.CpuidAccess.Rcx == 0) {
+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRdx
+ & CPUID_7_0_EDX_CET_IBT) {
+ reg_values[3].Reg32 |= CPUID_7_0_EDX_CET_IBT;
+ } else {
+ reg_values[3].Reg32 &= ~CPUID_7_0_EDX_CET_IBT;
+ }
+
+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+ & CPUID_7_0_ECX_CET_SHSTK) {
+ reg_values[2].Reg32 |= CPUID_7_0_ECX_CET_SHSTK;
+ } else {
+ reg_values[2].Reg32 &= ~CPUID_7_0_ECX_CET_SHSTK;
+ }
+
+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+ & CPUID_7_0_ECX_OSPKE) {
+ reg_values[2].Reg32 |= CPUID_7_0_ECX_OSPKE;
+ } else {
+ reg_values[2].Reg32 &= ~CPUID_7_0_ECX_OSPKE;
+ }
+ }
+
+ /* OSXSAVE is dynamic. Do this instead of syncing CR4 */
+ if (vcpu->exit_ctx.CpuidAccess.Rax == 1) {
+ if (vcpu->exit_ctx.CpuidAccess.DefaultResultRcx
+ & CPUID_EXT_OSXSAVE) {
+ reg_values[2].Reg32 |= CPUID_EXT_OSXSAVE;
+ } else {
+ reg_values[2].Reg32 &= ~CPUID_EXT_OSXSAVE;
+ }
}
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(
@@ -2324,6 +2387,45 @@ error:
return ret;
}
+static void whpx_cpu_xsave_init(void)
+{
+ static bool first = true;
+ int i;
+
+ if (!first) {
+ return;
+ }
+ first = false;
+
+ /* x87 and SSE states are in the legacy region of the XSAVE area. */
+ x86_ext_save_areas[XSTATE_FP_BIT].offset = 0;
+ x86_ext_save_areas[XSTATE_SSE_BIT].offset = 0;
+
+ for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) {
+ ExtSaveArea *esa = &x86_ext_save_areas[i];
+
+ if (esa->size) {
+ int sz = whpx_get_supported_cpuid(0xd, i, R_EAX);
+ if (sz != 0) {
+ assert(esa->size == sz);
+ esa->offset = whpx_get_supported_cpuid(0xd, i, R_EBX);
+ }
+ }
+ }
+}
+
+static void whpx_cpu_max_instance_init(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ env->cpuid_min_level =
+ whpx_get_supported_cpuid(0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ whpx_get_supported_cpuid(0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ whpx_get_supported_cpuid(0xC0000000, 0, R_EAX);
+}
+
static PropValue whpx_default_props[] = {
{ "x2apic", "on" },
{ NULL, NULL },
@@ -2333,9 +2435,18 @@ static PropValue whpx_default_props[] = {
void whpx_cpu_instance_init(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
+ X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
host_cpu_instance_init(cpu);
x86_cpu_apply_props(cpu, whpx_default_props);
+
+ if (!whpx_is_legacy_os() && xcc->max_features) {
+ whpx_cpu_max_instance_init(cpu);
+ }
+
+ if (!whpx_is_legacy_os()) {
+ whpx_cpu_xsave_init();
+ }
}
/*
@@ -2353,8 +2464,12 @@ int whpx_accel_init(AccelState *as, MachineState *ms)
WHV_CAPABILITY_FEATURES features = {0};
WHV_PROCESSOR_FEATURES_BANKS processor_features;
WHV_PROCESSOR_PERFMON_FEATURES perfmon_features;
- UINT32 cpuidExitList[] = {1};
- UINT32 cpuidExitList_nohyperv[] = {1, 0x40000000, 0x40000001, 0x40000010};
+
+ UINT32 cpuidExitList[] = {0x0, 0x1, 0x6, 0x7, 0x14, 0x24, 0x29, 0x1E,
+ 0x40000000, 0x40000001, 0x40000010, 0x80000000, 0x80000001,
+ 0x80000002, 0x80000003, 0x80000004, 0x80000007, 0x80000008,
+ 0x8000000A, 0x80000021, 0x80000022, 0xC0000000, 0xC0000001};
+ UINT32 cpuidExitList_legacy_os[] = {1, 0x40000000, 0x40000001, 0x40000010};
whpx = &whpx_global;
@@ -2610,7 +2725,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)
hr = whp_dispatch.WHvSetPartitionProperty(
whpx->partition,
WHvPartitionPropertyCodeCpuidExitList,
- whpx->hyperv_enlightenments_enabled ? cpuidExitList : cpuidExitList_nohyperv,
+ !whpx_is_legacy_os() ? cpuidExitList : cpuidExitList_legacy_os,
RTL_NUMBER_OF(cpuidExitList) * sizeof(UINT32));
if (FAILED(hr)) {
--
2.50.1 (Apple Git-155)
next prev parent reply other threads:[~2026-04-20 10:47 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 10:42 [PATCH v2 00/38] WHPX x86 updates for QEMU 11.1 Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 01/38] target/i386: emulate: include name of unhandled instruction Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 02/38] whpx: i386: x2apic emulation Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 03/38] whpx: i386: wire up feature probing Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 04/38] whpx: i386: disable TbFlushHypercalls for emulated LAPIC Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 05/38] whpx: i386: enable x2apic by default for user-mode LAPIC Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 06/38] whpx: i386: reintroduce enlightenments for Windows 10 Mohamed Mediouni
2026-04-20 10:42 ` Mohamed Mediouni [this message]
2026-04-20 10:42 ` [PATCH v2 08/38] whpx: i386: kernel-irqchip=off fixes Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 09/38] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 10/38] whpx: i386: disable kernel-irqchip on Windows 10 when PIC enabled Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 11/38] whpx: i386: IO port fast path cleanup Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 12/38] whpx: i386: disable enlightenments and LAPIC for isapc Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 13/38] whpx: i386: interrupt priority support Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 14/38] hw/intc: apic: disallow APIC reads when disabled Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 15/38] whpx: i386: fix CPUID[1:EDX].APIC reporting Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 16/38] whpx: i386: set apicbase value only on success Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 17/38] whpx: i386: unknown MSR configurability Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 18/38] whpx: i386: enable GuestIdleReg enlightenment Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 19/38] whpx: i386: tighten APIC base validity check Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 20/38] whpx: i386: ignore vpassist when kernel-irqchip=off Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 21/38] target: i386: HLT type that ignores EFLAGS.IF Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 22/38] whpx: i386: add HV_X64_MSR_GUEST_IDLE when !kernel-irqchip Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 23/38] whpx: i386: one more CPUID Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 24/38] whpx: i386: some x2APIC awareness Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 25/38] whpx: i386: set WHvX64RegisterInitialApicId Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 26/38] whpx: i386: Pause VM on fatal exception to be able to inspect state Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 27/38] target/i386: emulate: use exception_payload for fault address Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 28/38] whpx: i386: CPU features support for Windows 10 Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 29/38] target/i386: make xsave_buf present unconditionally Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 30/38] target/i386: add de/compaction to xsave_helper Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 31/38] whpx: xsave support Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 32/38] whpx: i386: set APIC ID only when APIC present Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 33/38] whpx: i386: update migration blocker message Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 34/38] whpx: i386: don't increment eip on MSR access raising GPF Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 35/38] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling Mohamed Mediouni
2026-04-20 11:27 ` Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 36/38] whpx: i386: add feature to intercept #GP MSR accesses Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 37/38] whpx: i386: intercept CPUID 0xD too Mohamed Mediouni
2026-04-20 10:42 ` [PATCH v2 38/38] whpx: i386: documentation update Mohamed Mediouni
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