[PULL 0/9] hex queue

[PULL 0/9] hex queue

[Brian Cain]

The following changes since commit bb230769b4d01de714bed686161ad39a8f4f3fd1:

  Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2026-04-22 14:30:04 -0400)

are available in the Git repository at:

  https://github.com/quic/qemu tags/pull-hex-20260423

for you to fetch changes up to b4bbd68882f24b0f99593b48fc50122e5dac5c41:

  target/hexagon: Change DisasContext packet type (2026-04-23 14:49:38 -0700)

----------------------------------------------------------------
Hexagon arch rev specific behavior

----------------------------------------------------------------
Brian Cain (1):
      tests/tcg/hexagon: Add test for revision-gated instruction decoding

Marco Liebel (1):
      target/hexagon: Change DisasContext packet type

Matheus Tavares Bernardino (1):
      Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

Taylor Simpson (6):
      Hexagon (target/hexagon) Properly handle Hexagon CPU version
      Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file
      Hexagon (target/hexagon) Add Hexagon definition field to DisasContext
      Hexagon (target/hexagon) Check each opcode against current CPU definition
      Hexagon (target/hexagon) Disassembly of invalid packets
      Hexagon (target/hexagon) Remove snprint_a_pkt_debug

 target/hexagon/cpu-qom.h             |  27 ++
 target/hexagon/cpu.h                 |   2 +
 target/hexagon/cpu_bits.h            |   4 +-
 target/hexagon/decode.h              |   2 +
 target/hexagon/gen_tcg.h             |   2 +-
 target/hexagon/macros.h              |   6 +-
 target/hexagon/printinsn.h           |   4 +-
 target/hexagon/translate.h           |   3 +-
 disas/hexagon.c                      |   3 +-
 linux-user/hexagon/elfload.c         |  43 ++-
 target/hexagon/cpu.c                 |  48 ++-
 target/hexagon/decode.c              |  58 +++-
 target/hexagon/genptr.c              |  14 +-
 target/hexagon/printinsn.c           |  40 +--
 target/hexagon/translate.c           | 114 +++----
 tests/tcg/hexagon/check_rev_gating.c | 141 ++++++++
 target/hexagon/tag_rev_info.c.inc    | 613 +++++++++++++++++++++++++++++++++++
 target/hexagon/gen_tcg_funcs.py      |   2 +-
 target/hexagon/hex_common.py         |   4 +-
 tests/tcg/hexagon/Makefile.target    |   6 +
 20 files changed, 976 insertions(+), 160 deletions(-)
 create mode 100644 tests/tcg/hexagon/check_rev_gating.c
 create mode 100644 target/hexagon/tag_rev_info.c.inc

[PULL 1/9] Hexagon (target/hexagon) Properly handle Hexagon CPU version

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

Add the following CPU versions that were previously missing
    v5
    v55
    v60
    v61
    v62
    v65

Create a CPUHexagonDef struct to represent the definition of a core
    Currently contains an enum with the known Hexagon CPU versions
Add a field to HexagonCPUClass to note the Hexagon definition

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu-qom.h | 27 +++++++++++++++++++++++
 target/hexagon/cpu.h     |  2 ++
 target/hexagon/cpu.c     | 46 ++++++++++++++++++++++++----------------
 3 files changed, 57 insertions(+), 18 deletions(-)

diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index 0b149bd5fea..6e1bb040704 100644
--- a/target/hexagon/cpu-qom.h
+++ b/target/hexagon/cpu-qom.h
@@ -11,11 +11,38 @@
 
 #include "hw/core/cpu.h"
 
+typedef enum {
+    HEX_VER_NONE = 0x00,
+    HEX_VER_V5 = 0x04,
+    HEX_VER_V55 = 0x05,
+    HEX_VER_V60 = 0x60,
+    HEX_VER_V61 = 0x61,
+    HEX_VER_V62 = 0x62,
+    HEX_VER_V65 = 0x65,
+    HEX_VER_V66 = 0x66,
+    HEX_VER_V67 = 0x67,
+    HEX_VER_V68 = 0x68,
+    HEX_VER_V69 = 0x69,
+    HEX_VER_V71 = 0x71,
+    HEX_VER_V73 = 0x73,
+    HEX_VER_ANY = 0xff,
+} HexagonVersion;
+
+typedef struct {
+    HexagonVersion hex_version;
+} HexagonCPUDef;
+
 #define TYPE_HEXAGON_CPU "hexagon-cpu"
 
 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
 
+#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME("v5")
+#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME("v55")
+#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME("v60")
+#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME("v61")
+#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME("v62")
+#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME("v65")
 #define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66")
 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
 #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 85afd592778..f99647dfb61 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -117,6 +117,8 @@ typedef struct HexagonCPUClass {
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
+
+    const HexagonCPUDef *hex_def;
 } HexagonCPUClass;
 
 struct ArchCPU {
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index ffd14bb4678..23ac91e7b47 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -27,13 +27,6 @@
 #include "exec/gdbstub.h"
 #include "accel/tcg/cpu-ops.h"
 
-static void hexagon_v66_cpu_init(Object *obj) { }
-static void hexagon_v67_cpu_init(Object *obj) { }
-static void hexagon_v68_cpu_init(Object *obj) { }
-static void hexagon_v69_cpu_init(Object *obj) { }
-static void hexagon_v71_cpu_init(Object *obj) { }
-static void hexagon_v73_cpu_init(Object *obj) { }
-
 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
 {
     ObjectClass *oc;
@@ -377,11 +370,21 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
     cc->tcg_ops = &hexagon_tcg_ops;
 }
 
-#define DEFINE_CPU(type_name, initfn)      \
-    {                                      \
-        .name = type_name,                 \
-        .parent = TYPE_HEXAGON_CPU,        \
-        .instance_init = initfn            \
+static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data)
+{
+    HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
+    /* Make sure all CPU models define a HexagonCPUDef */
+    g_assert(!object_class_is_abstract(c) && data != NULL);
+    mcc->hex_def = data;
+}
+
+#define DEFINE_CPU(type_name, version)         \
+    {                                          \
+        .name = type_name,                     \
+        .parent = TYPE_HEXAGON_CPU,            \
+        .class_data = &(const HexagonCPUDef) { \
+            .hex_version = version,            \
+        }                                      \
     }
 
 static const TypeInfo hexagon_cpu_type_infos[] = {
@@ -394,13 +397,20 @@ static const TypeInfo hexagon_cpu_type_infos[] = {
         .abstract = true,
         .class_size = sizeof(HexagonCPUClass),
         .class_init = hexagon_cpu_class_init,
+        .class_base_init = hexagon_cpu_class_base_init,
     },
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V66,              hexagon_v66_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              hexagon_v67_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V68,              hexagon_v68_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V69,              hexagon_v69_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V71,              hexagon_v71_cpu_init),
-    DEFINE_CPU(TYPE_HEXAGON_CPU_V73,              hexagon_v73_cpu_init),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V5,               HEX_VER_V5),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V55,              HEX_VER_V55),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V60,              HEX_VER_V60),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V61,              HEX_VER_V61),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V62,              HEX_VER_V62),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V65,              HEX_VER_V65),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V66,              HEX_VER_V66),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              HEX_VER_V67),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V68,              HEX_VER_V68),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V69,              HEX_VER_V69),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V71,              HEX_VER_V71),
+    DEFINE_CPU(TYPE_HEXAGON_CPU_V73,              HEX_VER_V73),
 };
 
 DEFINE_TYPES(hexagon_cpu_type_infos)
-- 
2.34.1

[PULL 2/9] Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

Return proper Hexagon CPU version from get_elf_cpu_model

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 linux-user/hexagon/elfload.c | 43 ++++++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/linux-user/hexagon/elfload.c b/linux-user/hexagon/elfload.c
index d8b545032ab..39b02018145 100644
--- a/linux-user/hexagon/elfload.c
+++ b/linux-user/hexagon/elfload.c
@@ -10,23 +10,32 @@ const char *get_elf_cpu_model(uint32_t eflags)
     static char buf[32];
     int err;
 
-    /* For now, treat anything newer than v5 as a v73 */
-    /* FIXME - Disable instructions that are newer than the specified arch */
-    if (eflags == 0x04 ||    /* v5  */
-        eflags == 0x05 ||    /* v55 */
-        eflags == 0x60 ||    /* v60 */
-        eflags == 0x61 ||    /* v61 */
-        eflags == 0x62 ||    /* v62 */
-        eflags == 0x65 ||    /* v65 */
-        eflags == 0x66 ||    /* v66 */
-        eflags == 0x67 ||    /* v67 */
-        eflags == 0x8067 ||  /* v67t */
-        eflags == 0x68 ||    /* v68 */
-        eflags == 0x69 ||    /* v69 */
-        eflags == 0x71 ||    /* v71 */
-        eflags == 0x8071 ||  /* v71t */
-        eflags == 0x73       /* v73 */
-       ) {
+    switch (eflags) {
+    case 0x04:
+        return "v5";
+    case 0x05:
+        return "v55";
+    case 0x60:
+        return "v60";
+    case 0x61:
+        return "v61";
+    case 0x62:
+        return "v62";
+    case 0x65:
+        return "v65";
+    case 0x66:
+        return "v66";
+    case 0x67:
+    case 0x8067:        /* v67t */
+        return "v67";
+    case 0x68:
+        return "v68";
+    case 0x69:
+        return "v69";
+    case 0x71:
+    case 0x8071:        /* v71t */
+        return "v71";
+    case 0x73:
         return "v73";
     }
 
-- 
2.34.1

[PULL 3/9] Hexagon (target/hexagon) Add Hexagon definition field to DisasContext

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

Initialize the field in hexagon_tr_init_disas_context

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/translate.h | 1 +
 target/hexagon/translate.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index b37cb492381..9cdcbd64164 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -30,6 +30,7 @@ typedef struct DisasContext {
     DisasContextBase base;
     Packet *pkt;
     Insn *insn;
+    const HexagonCPUDef *hex_def;
     uint32_t next_PC;
     uint32_t mem_idx;
     uint32_t num_packets;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 633401451d8..12c82fd6c5a 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
     ctx->branch_cond = TCG_COND_NEVER;
     ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);
     ctx->short_circuit = hex_cpu->short_circuit;
+    ctx->hex_def = HEXAGON_CPU_GET_CLASS(hex_cpu)->hex_def;
 }
 
 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.34.1

[PULL 4/9] Hexagon (target/hexagon) Introduce tag_rev_info.c.inc

[Brian Cain]

From: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>

Table that records which CPU revision introduced or removed
for each opcode

Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/tag_rev_info.c.inc | 613 ++++++++++++++++++++++++++++++
 1 file changed, 613 insertions(+)
 create mode 100644 target/hexagon/tag_rev_info.c.inc

diff --git a/target/hexagon/tag_rev_info.c.inc b/target/hexagon/tag_rev_info.c.inc
new file mode 100644
index 00000000000..11c90f86ad1
--- /dev/null
+++ b/target/hexagon/tag_rev_info.c.inc
@@ -0,0 +1,613 @@
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HEXAGON_TAG_ARCH_TABLE_H
+#define HEXAGON_TAG_ARCH_TABLE_H
+
+struct tag_rev_info { HexagonVersion introduced, removed; };
+
+static const struct tag_rev_info tag_rev_info[XX_LAST_OPCODE] = {
+    [A5_ACS] = { .introduced = HEX_VER_V55, .removed = HEX_VER_NONE },
+
+    [J2_jumpfpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumprfpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumprtpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [J2_jumptpt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_nac] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_p_xacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_nac] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [S6_rol_i_r_xacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_extractw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_lvsplatw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_and_n] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_not] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_or_n] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_scalar2] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_pred_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32Ub_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32Ub_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_new_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nqpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_new_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_npred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_nqpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_nt_qpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_pred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_ai] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_pi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vS32b_qpred_ppu] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsdiffw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vabsw_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddbnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddbq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddh_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddubsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vadduhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddw_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaddwsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_valignb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_valignbi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vand] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandqrt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandqrt_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandvrt] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vandvrt_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslw_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vaslwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhbrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhubrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhubsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrw_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwhrndsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwuhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vasrwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vassign] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavghrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgubrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavguh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavguhrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vavgwrnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vccombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcl0h] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcl0w] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcmov] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vcombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdeal] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealb4w] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdealvdd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdelta] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpybus_dv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhb_dv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhisat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhisat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsuisat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsuisat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsusat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhsusat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhvsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdmpyhvsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdsaduh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vdsaduh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqb_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqh_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_veqw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtb_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgth_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtub_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuh_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtuw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_and] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_or] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vgtw_xor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vhist] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vhistq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vinsertwr] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlalignb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlalignbi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlsrwv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvvb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_oracc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_oracc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmaxw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vminw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpabuuv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpahb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpahb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybusv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpybv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyewuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhsat_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhsrs] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhss] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyhvsrs] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyieoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiewuh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyih] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyih_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyihb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyihb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiowh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyiwh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_rnd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_rnd_sacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_sacc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyub_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyubv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyubv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuh_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuhv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmpyuhv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vmux] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnavgw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnccombine] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vncmov] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnormamth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnormamtw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vnot] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackhb_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackhub_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackwh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpackwuh_sat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vpopcounth] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrdelta] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybusv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpybv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyub_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrmpyubv_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vror] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundhub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vroundwuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrsadubi] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vrsadubi_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsathub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsatwh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuff] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshuffvdd] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoeb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoeh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vshufoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubb_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubbnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubbq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubh_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsububsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubuhw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubw] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubw_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwnq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwq] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwsat] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vsubwsat_dv] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vswap] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpybus] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpybus_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyhb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vtmpyhb_acc] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackob] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackoh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackub] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vunpackuh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vxor] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vzb] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+    [V6_vzh] = { .introduced = HEX_VER_V60, .removed = HEX_VER_NONE },
+
+    [A6_vminub_RdP] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [M6_vabsdiffb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [M6_vabsdiffub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vsplatrbp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vtrunehb_ppp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [S6_vtrunohb_ppp] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_lvsplatb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_lvsplath] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_pred_scalar2v2] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_shuffeqh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_shuffeqw] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_cur_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_cur_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_nt_tmp_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_npred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_ai] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_pi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vL32b_tmp_pred_ppu] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddbsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddcarry] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddclbh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddclbw] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddhw_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddubh_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vaddububb_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduhw_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduwsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vadduwsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandnqrt] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandnqrt_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandvnqv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vandvqv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasrhbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasruwuhrndsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vasrwuhrndsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlsrb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_nm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvb_oracci] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvvbi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_nm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwh_oracci] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vlutvwhi] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmaxb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vminb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpauhb] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpauhb_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyewuh_64] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyiwub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyiwub_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vmpyowh_64_acc] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vrounduhub] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vrounduwuh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsatuwuh] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubbsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubbsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubcarry] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubububb_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubuwsat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vsubuwsat_dv] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128m] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128q] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist128qm] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256q] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+    [V6_vwhist256q_sat] = { .introduced = HEX_VER_V62, .removed = HEX_VER_NONE },
+
+    [A6_vcmpbeq_notany] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_ai] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_pi] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vS32b_srls_ppu] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vabsb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vabsb_sat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vaslh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasrh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruhubrndsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruhubsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vasruwuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavgb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavgbrnd] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavguw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vavguwrnd] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermhwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vgathermwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vlut4] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpabuu] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpabuu_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpahhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpauhuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpsuhuhsat] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyh_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyuhe] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vmpyuhe_acc] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vnavgb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqb] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vprefixqw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermh] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermh_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhw_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermhwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermw] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermw_add] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+    [V6_vscattermwq] = { .introduced = HEX_VER_V65, .removed = HEX_VER_NONE },
+
+    [F2_dfadd] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [F2_dfsub] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [M2_mnaci] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [S2_mask] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vaddcarryo] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vaddcarrysat] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vasr_into] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vrotr] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vsatdw] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+    [V6_vsubcarryo] = { .introduced = HEX_VER_V66, .removed = HEX_VER_NONE },
+
+    [A7_clip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_croundd_ri] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_croundd_rr] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [A7_vclip] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmax] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmin] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyfix] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyhh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpylh] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [F2_dfmpyll] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [J2_callrh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
+    [J2_jumprh] = { .introduced = 0x73, .removed = HEX_VER_NONE },
+    [L2_loadw_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [L4_loadd_aq] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [M7_dcmpyiw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiw_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyiwc_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrw_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_dcmpyrwc_acc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiw_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyiwc_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrw] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrw_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrwc] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [M7_wcmpyrwc_rnd] = { .introduced = HEX_VER_V67, .removed = HEX_VER_NONE },
+    [R6_release_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [R6_release_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S2_storew_rl_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S2_storew_rl_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S4_stored_rl_at_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [S4_stored_rl_st_vi] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyhubs10] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyhubs10_vxx] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyvubs10] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_v6mpyvubs10_vxx] = { .introduced = HEX_VER_V68, .removed = HEX_VER_NONE },
+    [V6_vasrvuhubrndsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvuhubsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvwuhrndsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vasrvwuhsat] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vassign_tmp] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vcombine_tmp] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+    [V6_vmpyuhvs] = { .introduced = HEX_VER_V69, .removed = HEX_VER_NONE },
+};
+
+#endif /* HEXAGON_TAG_ARCH_TABLE_H */
-- 
2.34.1

[PULL 5/9] Hexagon (target/hexagon) Check each opcode against current CPU definition

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

During decoding, check that the opcode is supported in the current
Hexagon CPU definition

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/decode.h |  2 ++
 target/hexagon/decode.c | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/target/hexagon/decode.h b/target/hexagon/decode.h
index 3f3012b978d..d4b049961ed 100644
--- a/target/hexagon/decode.h
+++ b/target/hexagon/decode.h
@@ -30,4 +30,6 @@ void decode_send_insn_to(Packet *packet, int start, int newloc);
 int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
                   Packet *pkt, bool disas_only);
 
+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def);
+
 #endif
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index dbc9c630e82..b8a1cd5b12b 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -647,6 +647,22 @@ decode_set_slot_number(Packet *pkt)
     return has_valid_slot_assignment(pkt);
 }
 
+bool opcode_supported(uint16_t opcode, const HexagonCPUDef *hex_def)
+{
+    HexagonVersion hex_version = hex_def->hex_version;
+#include "tag_rev_info.c.inc"
+
+    struct tag_rev_info info = tag_rev_info[opcode];
+    if (hex_version == HEX_VER_ANY) {
+        return true;
+    }
+    if ((info.introduced != HEX_VER_NONE && hex_version < info.introduced) ||
+        (info.removed != HEX_VER_NONE && hex_version >= info.removed)) {
+        return false;
+    }
+    return true;
+}
+
 /*
  * Check for GPR write conflicts in the packet.
  * A conflict exists when a register is written by more than one instruction
@@ -746,6 +762,17 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
         /* Ran out of words! */
         return 0;
     }
+
+    /*
+     * Check that all the opcodes are supported in this Hexagon definition
+     * If not, return decode error
+     */
+    for (i = 0; i < num_insns; i++) {
+        if (!opcode_supported(pkt->insn[i].opcode, ctx->hex_def)) {
+            return 0;
+        }
+    }
+
     pkt->encod_pkt_size_in_bytes = words_read * 4;
     pkt->pkt_has_hvx = false;
     for (i = 0; i < num_insns; i++) {
-- 
2.34.1

[PULL 6/9] Hexagon (target/hexagon) Disassembly of invalid packets

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

We pass the Hexagon CPU definition to disassemble_hexagon.  This allows
decode_packet to know if the opcodes are supported.

Note that we print valid instructions in a packet when one or more is
invalid.  Rather than this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		<invalid>
0x00021294:  0x1e03edf0		<invalid> }

We print this
0x0002128c:  0x1eae4fec	{	<invalid>
0x00021290:  0x1c434c04		V4.w = vadd(V12.w,V3.w)
0x00021294:  0x1e03edf0		V16 = V13 }

Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Co-authored-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu_bits.h  |  4 +++-
 target/hexagon/printinsn.h |  3 ++-
 disas/hexagon.c            |  3 ++-
 target/hexagon/cpu.c       |  2 ++
 target/hexagon/decode.c    | 25 +++++++++++++++++++++----
 target/hexagon/printinsn.c |  9 +++++++--
 6 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 19beca81c0c..aaac6b9ea64 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -19,6 +19,7 @@
 #define HEXAGON_CPU_BITS_H
 
 #include "qemu/bitops.h"
+#include "cpu-qom.h"
 
 #define PCALIGN 4
 #define PCALIGN_MASK (PCALIGN - 1)
@@ -65,6 +66,7 @@ static inline bool is_packet_end(uint32_t endocing)
     return ((bits == 0x3) || (bits == 0x0));
 }
 
-int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf);
+int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc, GString *buf,
+                        const HexagonCPUDef *hex_def);
 
 #endif
diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
index 2ecd1731d03..6f84ef93c3b 100644
--- a/target/hexagon/printinsn.h
+++ b/target/hexagon/printinsn.h
@@ -18,10 +18,11 @@
 #ifndef HEXAGON_PRINTINSN_H
 #define HEXAGON_PRINTINSN_H
 
+#include "cpu-qom.h"
 #include "insn.h"
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
-                         target_ulong pc);
+                         target_ulong pc, const HexagonCPUDef *hex_def);
 void snprint_a_pkt_debug(GString *buf, Packet *pkt);
 
 #endif
diff --git a/disas/hexagon.c b/disas/hexagon.c
index c1a4ffc5f6b..36b8321c26a 100644
--- a/disas/hexagon.c
+++ b/disas/hexagon.c
@@ -31,6 +31,7 @@
 
 int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
 {
+    const HexagonCPUDef *hex_def = (const HexagonCPUDef *)info->target_info;
     uint32_t words[PACKET_WORDS_MAX];
     bool found_end = false;
     GString *buf;
@@ -58,7 +59,7 @@ int print_insn_hexagon(bfd_vma memaddr, struct disassemble_info *info)
     }
 
     buf = g_string_sized_new(PACKET_BUFFER_LEN);
-    len = disassemble_hexagon(words, i, memaddr, buf);
+    len = disassemble_hexagon(words, i, memaddr, buf, hex_def);
     (*info->fprintf_func)(info->stream, "%s", buf->str);
     g_string_free(buf, true);
 
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 23ac91e7b47..2c53f2c2836 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -297,8 +297,10 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
 static void hexagon_cpu_disas_set_info(const CPUState *cs,
                                        disassemble_info *info)
 {
+    const HexagonCPU *cpu = HEXAGON_CPU(cs);
     info->print_insn = print_insn_hexagon;
     info->endian = BFD_ENDIAN_LITTLE;
+    info->target_info = HEXAGON_CPU_GET_CLASS(cpu)->hex_def;
 }
 
 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index b8a1cd5b12b..c4cf430e5a2 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -828,19 +828,36 @@ int decode_packet(DisasContext *ctx, int max_words, const uint32_t *words,
 
 /* Used for "-d in_asm" logging */
 int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
-                        GString *buf)
+                        GString *buf, const HexagonCPUDef  *hex_def)
 {
+    HexagonCPUDef any_def = {
+        .hex_version = HEX_VER_ANY,  /* Allow decode to accept anything */
+    };
     DisasContext ctx;
     Packet pkt;
 
     memset(&ctx, 0, sizeof(DisasContext));
+    ctx.hex_def = &any_def;
     ctx.pkt = &pkt;
 
     if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {
-        snprint_a_pkt_disas(buf, &pkt, words, pc);
+        snprint_a_pkt_disas(buf, &pkt, words, pc, hex_def);
         return pkt.encod_pkt_size_in_bytes;
     } else {
-        g_string_assign(buf, "<invalid>");
-        return 0;
+        for (int i = 0; i < nwords; i++) {
+            g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]);
+            if (i == 0) {
+                g_string_append(buf, "{");
+            }
+            g_string_append(buf, "\t");
+            g_string_append(buf, "<invalid>");
+            if (i < nwords - 1) {
+                pc += 4;
+                g_string_append_printf(buf, "\n0x" TARGET_FMT_lx ":  ",
+                                       (target_ulong)pc);
+            }
+        }
+        g_string_append(buf, " }");
+        return nwords * sizeof(uint32_t);
     }
 }
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
index 4865cdd133b..22b305f018e 100644
--- a/target/hexagon/printinsn.c
+++ b/target/hexagon/printinsn.c
@@ -21,6 +21,7 @@
 #include "insn.h"
 #include "reg_fields.h"
 #include "internal.h"
+#include "decode.h"
 
 static const char *sreg2str(unsigned int reg)
 {
@@ -51,7 +52,7 @@ static void snprintinsn(GString *buf, Insn *insn)
 }
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
-                         target_ulong pc)
+                         target_ulong pc, const HexagonCPUDef *hex_def)
 {
     bool has_endloop0 = false;
     bool has_endloop1 = false;
@@ -83,7 +84,11 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
         }
 
         g_string_append(buf, "\t");
-        snprintinsn(buf, &(pkt->insn[i]));
+        if (opcode_supported(pkt->insn[i].opcode, hex_def)) {
+            snprintinsn(buf, &(pkt->insn[i]));
+        } else {
+            g_string_append(buf, "<invalid>");
+        }
 
         if (i < pkt->num_insns - 1) {
             /*
-- 
2.34.1

[PULL 7/9] tests/tcg/hexagon: Add test for revision-gated instruction decoding

[Brian Cain]

Add check_rev_gating, a linux-user test that verifies the decoder
rejects instructions from a newer CPU revision than the one selected
by the ELF binary's e_flags.

Co-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Co-authored-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 tests/tcg/hexagon/check_rev_gating.c | 141 +++++++++++++++++++++++++++
 tests/tcg/hexagon/Makefile.target    |   6 ++
 2 files changed, 147 insertions(+)
 create mode 100644 tests/tcg/hexagon/check_rev_gating.c

diff --git a/tests/tcg/hexagon/check_rev_gating.c b/tests/tcg/hexagon/check_rev_gating.c
new file mode 100644
index 00000000000..26b66f54552
--- /dev/null
+++ b/tests/tcg/hexagon/check_rev_gating.c
@@ -0,0 +1,141 @@
+/*
+ * Test that instructions from a newer revision than the running CPU
+ * are rejected with SIGILL.
+ *
+ * Compiled with -mv66 so that e_flags selects CPU v66. The test embeds
+ * a v68 instruction (L2_loadw_aq: "r0 = memw_aq(r0)") via .word
+ * encoding. The revision-gated decoder must reject it, and linux-user
+ * must deliver SIGILL.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static void *resume_pc;
+static int signals_handled;
+static int expected_signals;
+
+static void handle_sigill(int sig, siginfo_t *info, void *puc)
+{
+    ucontext_t *uc = (ucontext_t *)puc;
+
+    if (sig != SIGILL) {
+        _exit(EXIT_FAILURE);
+    }
+
+    uc->uc_mcontext.r0 = SIGILL;
+    uc->uc_mcontext.pc = (unsigned long)resume_pc;
+    signals_handled++;
+}
+
+/*
+ * Try to execute an instruction introduced after v66
+ * On a v66 CPU this must raise SIGILL.
+ *
+ * Since we are building for v66, the assembler will reject
+ * the instructions, so introduce them with .word.
+ */
+#define TRY_FUNC(NAME, WORD) \
+static int try_##NAME(void) \
+{ \
+    int sig; \
+    expected_signals++; \
+    asm volatile( \
+        "r0 = #0\n" \
+        "r1 = ##1f\n" \
+        "memw(%1) = r1\n" \
+        WORD \
+        "1:\n" \
+        "%0 = r0\n" \
+        : "=r"(sig) \
+        : "r"(&resume_pc) \
+        : "r0", "r1", "memory"); \
+    return sig; \
+}
+
+TRY_FUNC(v68_loadw_aq,
+         ".word 0x9200c800    /* { r0 = memw_aq(r0) } */\n")
+TRY_FUNC(v68_loadd_aq,
+         ".word 0x9201d800    /* r1:0 = memd_aq(r1) */\n")
+TRY_FUNC(v68_release_at,
+         ".word 0xa0e0c00c    /* release(r0):at */\n")
+TRY_FUNC(v68_release_st,
+         ".word 0xa0e0c02c    /* release(r0):st */\n")
+TRY_FUNC(v68_storew_rl_at,
+         ".word 0xa0a0c108    /* memw_rl(r0):at = r1 */\n")
+TRY_FUNC(v68_stored_rl_at,
+         ".word 0xa0e2c008    /* memd_rl(r2):at = r1:0 */\n")
+TRY_FUNC(v68_storew_rl_st,
+         ".word 0xa0a0c128    /* memw_rl(r0):st = r1 */\n")
+TRY_FUNC(v68_stored_rl_st,
+         ".word 0xa0e2c028    /* memd_rl(r2):st = r1:0 */\n")
+
+TRY_FUNC(v68hvx_v6mpy,
+         ".word 0x1f42e424    /* v5:4.w = v6mpy(v5:4.ub, v3:2.b, #1):v */\n")
+
+TRY_FUNC(v69hvx_vasrvuhubrndsat,
+         ".word 0x1d06c465    /* v5.ub = vasr(v5:4.uh, v6.ub):rnd:sat */\n")
+TRY_FUNC(v69hvx_vasrvuhubsat,
+         ".word 0x1d06c445    /* v5.ub = vasr(v5:4.uh, v6.ub):sat */\n")
+TRY_FUNC(v69hvx_vasrvwuhrndsat,
+         ".word 0x1d06c425    /* v5.uh = vasr(v5:4.w, v6.uh):rnd:sat */\n")
+TRY_FUNC(v69hvx_vasrvwuhsat,
+         ".word 0x1d06c405    /* v5.uh = vasr(v5:4.w, v6.uh):sat */\n")
+TRY_FUNC(v69hvx_vassign_tmp,
+         ".word 0x1e014dcc    /* { v12.tmp = v13 */\n"
+         ".word 0x1c43cc04    /*    v4.w = vadd(v12.w, v3.w) } */\n")
+TRY_FUNC(v69hvx_vcombine_tmp,
+         ".word 0x1eae4fec    /* { v13:12.tmp = vcombine(v15, v14) */\n"
+         ".word 0x1c434c04    /*   v4.w = vadd(v12.w, v3.w) */\n"
+         ".word 0x1e03edf0    /*   v16 = v13 } */\n")
+TRY_FUNC(v69hvx_vmpyuhvs,
+         ".word 0x1fc5e4e4    /* v4.uh = vmpy(V4.uh, v5.uh):>>16 */\n")
+
+TRY_FUNC(v73_callrh,
+         ".word 0x50c5c000    /* callrh r5 */\n")
+TRY_FUNC(v73_jumprh,
+         ".word 0x52c0c000    /* jumprh r0 */\n")
+
+int main(void)
+{
+    struct sigaction act;
+
+    memset(&act, 0, sizeof(act));
+    act.sa_sigaction = handle_sigill;
+    act.sa_flags = SA_SIGINFO;
+    assert(sigaction(SIGILL, &act, NULL) == 0);
+
+    assert(try_v68_loadw_aq() == SIGILL);
+    assert(try_v68_loadd_aq() == SIGILL);
+    assert(try_v68_release_at() == SIGILL);
+    assert(try_v68_release_st() == SIGILL);
+    assert(try_v68_storew_rl_at() == SIGILL);
+    assert(try_v68_stored_rl_at() == SIGILL);
+    assert(try_v68_storew_rl_st() == SIGILL);
+    assert(try_v68_stored_rl_st() == SIGILL);
+
+    assert(try_v68hvx_v6mpy() == SIGILL);
+
+    assert(try_v69hvx_vasrvuhubrndsat() == SIGILL);
+    assert(try_v69hvx_vasrvuhubsat() == SIGILL);
+    assert(try_v69hvx_vasrvwuhrndsat() == SIGILL);
+    assert(try_v69hvx_vasrvwuhsat() == SIGILL);
+    assert(try_v69hvx_vassign_tmp() == SIGILL);
+    assert(try_v69hvx_vcombine_tmp() == SIGILL);
+    assert(try_v69hvx_vmpyuhvs() == SIGILL);
+
+    assert(try_v73_callrh() == SIGILL);
+    assert(try_v73_jumprh() == SIGILL);
+
+    assert(signals_handled == expected_signals);
+
+    puts("PASS");
+    return EXIT_SUCCESS;
+}
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index 549c95082f6..09f0502abc5 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -81,6 +81,7 @@ HEX_TESTS += test_vminh
 HEX_TESTS += test_vpmpyh
 HEX_TESTS += test_vspliceb
 
+HEX_TESTS += check_rev_gating
 HEX_TESTS += test_pnew_jump_loads
 
 HEX_TESTS += v68_scalar
@@ -109,6 +110,11 @@ reg_mut: reg_mut.c hex_test.h
 test_pnew_jump_loads: test_pnew_jump_loads.c hex_test.h
 unaligned_pc: unaligned_pc.c
 
+# Compile for v66 so that the ELF selects a v66 CPU; the test then
+# exercises revision gating by executing a v68 .word instruction.
+check_rev_gating: check_rev_gating.c
+	$(CC) $(CFLAGS) -mv66 -O2 $< -o $@ $(LDFLAGS)
+
 # This test has to be compiled for the -mv67t target
 usr: usr.c hex_test.h
 	$(CC) $(CFLAGS) -mv67t -O2 -Wno-inline-asm -Wno-expansion-to-defined $< -o $@ $(LDFLAGS)
-- 
2.34.1

[PULL 8/9] Hexagon (target/hexagon) Remove snprint_a_pkt_debug

[Brian Cain]

From: Taylor Simpson <ltaylorsimpson@gmail.com>

Function is not used

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/printinsn.h |  1 -
 target/hexagon/printinsn.c | 31 -------------------------------
 2 files changed, 32 deletions(-)

diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
index 6f84ef93c3b..de962b5f2e6 100644
--- a/target/hexagon/printinsn.h
+++ b/target/hexagon/printinsn.h
@@ -23,6 +23,5 @@
 
 void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
                          target_ulong pc, const HexagonCPUDef *hex_def);
-void snprint_a_pkt_debug(GString *buf, Packet *pkt);
 
 #endif
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
index 22b305f018e..a7e46f4bcd9 100644
--- a/target/hexagon/printinsn.c
+++ b/target/hexagon/printinsn.c
@@ -118,34 +118,3 @@ void snprint_a_pkt_disas(GString *buf, Packet *pkt, uint32_t *words,
         g_string_append(buf, "  :endloop01");
     }
 }
-
-void snprint_a_pkt_debug(GString *buf, Packet *pkt)
-{
-    int slot, opcode;
-
-    if (pkt->num_insns > 1) {
-        g_string_append(buf, "\n{\n");
-    }
-
-    for (int i = 0; i < pkt->num_insns; i++) {
-        if (pkt->insn[i].part1) {
-            continue;
-        }
-        g_string_append(buf, "\t");
-        snprintinsn(buf, &(pkt->insn[i]));
-
-        if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
-            g_string_append(buf, " //subinsn");
-        }
-        if (pkt->insn[i].extension_valid) {
-            g_string_append(buf, " //constant extended");
-        }
-        slot = pkt->insn[i].slot;
-        opcode = pkt->insn[i].opcode;
-        g_string_append_printf(buf, " //slot=%d:tag=%s\n",
-                               slot, opcode_names[opcode]);
-    }
-    if (pkt->num_insns > 1) {
-        g_string_append(buf, "}\n");
-    }
-}
-- 
2.34.1

[PULL 9/9] target/hexagon: Change DisasContext packet type

[Brian Cain]

From: Marco Liebel <marco.liebel@oss.qualcomm.com>

The pkt variable inside DisasContext is of type Packet * and gets
assigned to a local variable in decode_and_translate_packet. Right now
there seems to be no problem with it but future changes to e.g.
hexagon_tr_transalte_packet are potentially dangerous if pkt is accessed
after the local variable goes out of scope.

Since packets are being translated one at a time, the type of pkt can be
changed to just Packet to avoid risk of having a dangling pointer.

Signed-off-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/gen_tcg.h        |   2 +-
 target/hexagon/macros.h         |   6 +-
 target/hexagon/translate.h      |   2 +-
 target/hexagon/decode.c         |   8 +--
 target/hexagon/genptr.c         |  14 ++--
 target/hexagon/translate.c      | 113 ++++++++++++++------------------
 target/hexagon/gen_tcg_funcs.py |   2 +-
 target/hexagon/hex_common.py    |   4 +-
 8 files changed, 66 insertions(+), 85 deletions(-)

diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 1e0cc3b29a8..0159e5c2d5f 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -1343,7 +1343,7 @@
 #define fGEN_TCG_J2_trap0(SHORTCODE) \
     do { \
         uiV = uiV; \
-        tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
+        tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt.pc); \
         TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \
         gen_helper_raise_exception(tcg_env, excp); \
     } while (0)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 6c2862a2320..eebfe1e5ed9 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -83,7 +83,7 @@
  */
 #define CHECK_NOSHUF(VA, SIZE) \
     do { \
-        if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
+        if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \
             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
             process_store(ctx, 1); \
         } \
@@ -94,11 +94,11 @@
         TCGLabel *noshuf_label = gen_new_label(); \
         tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \
         GET_EA; \
-        if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
+        if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \
             probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
         } \
         gen_set_label(noshuf_label); \
-        if (insn->slot == 0 && ctx->pkt->pkt_has_scalar_store_s1) { \
+        if (insn->slot == 0 && ctx->pkt.pkt_has_scalar_store_s1) { \
             process_store(ctx, 1); \
         } \
     } while (0)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 9cdcbd64164..1fc185e3edd 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -28,7 +28,7 @@
 
 typedef struct DisasContext {
     DisasContextBase base;
-    Packet *pkt;
+    Packet pkt;
     Insn *insn;
     const HexagonCPUDef *hex_def;
     uint32_t next_PC;
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index c4cf430e5a2..15954518b83 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -834,15 +834,13 @@ int disassemble_hexagon(uint32_t *words, int nwords, bfd_vma pc,
         .hex_version = HEX_VER_ANY,  /* Allow decode to accept anything */
     };
     DisasContext ctx;
-    Packet pkt;
 
     memset(&ctx, 0, sizeof(DisasContext));
     ctx.hex_def = &any_def;
-    ctx.pkt = &pkt;
 
-    if (decode_packet(&ctx, nwords, words, &pkt, true) > 0) {
-        snprint_a_pkt_disas(buf, &pkt, words, pc, hex_def);
-        return pkt.encod_pkt_size_in_bytes;
+    if (decode_packet(&ctx, nwords, words, &ctx.pkt, true) > 0) {
+        snprint_a_pkt_disas(buf, &ctx.pkt, words, pc, hex_def);
+        return ctx.pkt.encod_pkt_size_in_bytes;
     } else {
         for (int i = 0; i < nwords; i++) {
             g_string_append_printf(buf, "0x" TARGET_FMT_lx "\t", words[i]);
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index c7b9436c8d4..5d5adace4b3 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -382,7 +382,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
 static TCGv gen_slotval(DisasContext *ctx)
 {
     int slotval =
-        (ctx->pkt->pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
+        (ctx->pkt.pkt_has_scalar_store_s1 & 1) | (ctx->insn->slot << 1);
     return tcg_constant_tl(slotval);
 }
 #endif
@@ -458,7 +458,7 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,
         tcg_gen_brcondi_tl(cond, pred, 1, pred_false);
     }
 
-    if (ctx->pkt->pkt_has_multi_cof) {
+    if (ctx->pkt.pkt_has_multi_cof) {
         /* If there are multiple branches in a packet, ignore the second one */
         tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC],
                            ctx->branch_taken, tcg_constant_tl(0),
@@ -476,8 +476,8 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,
 static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,
                                    TCGCond cond, TCGv pred)
 {
-    target_ulong dest = ctx->pkt->pc + pc_off;
-    if (ctx->pkt->pkt_has_multi_cof) {
+    target_ulong dest = ctx->pkt.pc + pc_off;
+    if (ctx->pkt.pkt_has_multi_cof) {
         gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred);
     } else {
         /* Defer this jump to the end of the TB */
@@ -528,7 +528,7 @@ static inline void gen_loop0r(DisasContext *ctx, TCGv RsV, int riV)
     fIMMEXT(riV);
     fPCALIGN(riV);
     tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
-    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt.pc + riV);
     gen_set_usr_fieldi(ctx, USR_LPCFG, 0);
 }
 
@@ -542,7 +542,7 @@ static inline void gen_loop1r(DisasContext *ctx, TCGv RsV, int riV)
     fIMMEXT(riV);
     fPCALIGN(riV);
     tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC1), RsV);
-    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt->pc + riV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA1), ctx->pkt.pc + riV);
 }
 
 static void gen_loop1i(DisasContext *ctx, int count, int riV)
@@ -555,7 +555,7 @@ static void gen_ploopNsr(DisasContext *ctx, int N, TCGv RsV, int riV)
     fIMMEXT(riV);
     fPCALIGN(riV);
     tcg_gen_mov_tl(get_result_gpr(ctx, HEX_REG_LC0), RsV);
-    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt->pc + riV);
+    tcg_gen_movi_tl(get_result_gpr(ctx, HEX_REG_SA0), ctx->pkt.pc + riV);
     gen_set_usr_fieldi(ctx, USR_LPCFG, N);
     gen_pred_write(ctx, 3, tcg_constant_tl(0));
 }
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 12c82fd6c5a..f26281e6711 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -156,8 +156,6 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
 
 static void gen_end_tb(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-
     gen_exec_counters(ctx);
 
     if (ctx->branch_cond != TCG_COND_NEVER) {
@@ -171,7 +169,7 @@ static void gen_end_tb(DisasContext *ctx)
             gen_goto_tb(ctx, 0, ctx->branch_dest, true);
         }
     } else if (ctx->is_tight_loop &&
-               pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) {
+               ctx->pkt.insn[ctx->pkt.num_insns - 1].opcode == J2_endloop0) {
         /*
          * When we're in a tight loop, we defer the endloop0 processing
          * to take advantage of direct block chaining
@@ -266,11 +264,9 @@ static bool need_slot_cancelled(Packet *pkt)
 
 static bool need_next_PC(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-
     /* Check for conditional control flow or HW loop end */
-    for (int i = 0; i < pkt->num_insns; i++) {
-        uint16_t opcode = pkt->insn[i].opcode;
+    for (int i = 0; i < ctx->pkt.num_insns; i++) {
+        uint16_t opcode = ctx->pkt.insn[i].opcode;
         if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) {
             return true;
         }
@@ -353,8 +349,6 @@ static bool pkt_raises_exception(Packet *pkt)
 
 static bool need_commit(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-
     /*
      * If the short-circuit property is set to false, we'll always do the commit
      */
@@ -362,7 +356,7 @@ static bool need_commit(DisasContext *ctx)
         return true;
     }
 
-    if (pkt_raises_exception(pkt)) {
+    if (pkt_raises_exception(&ctx->pkt)) {
         return true;
     }
 
@@ -409,11 +403,10 @@ static void mark_implicit_writes(DisasContext *ctx)
 
 static void analyze_packet(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
     ctx->read_after_write = false;
     ctx->has_hvx_overlap = false;
-    for (int i = 0; i < pkt->num_insns; i++) {
-        Insn *insn = &pkt->insn[i];
+    for (int i = 0; i < ctx->pkt.num_insns; i++) {
+        Insn *insn = &ctx->pkt.insn[i];
         ctx->insn = insn;
         if (opcode_analyze[insn->opcode]) {
             opcode_analyze[insn->opcode](ctx);
@@ -425,8 +418,7 @@ static void analyze_packet(DisasContext *ctx)
 
 static void gen_start_packet(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-    target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
+    target_ulong next_PC = ctx->base.pc_next + ctx->pkt.encod_pkt_size_in_bytes;
     int i;
 
     /* Clear out the disassembly context */
@@ -468,13 +460,13 @@ static void gen_start_packet(DisasContext *ctx)
     bitmap_zero(ctx->pregs_written, NUM_PREGS);
 
     /* Initialize the runtime state for packet semantics */
-    if (need_slot_cancelled(pkt)) {
+    if (need_slot_cancelled(&ctx->pkt)) {
         tcg_gen_movi_tl(hex_slot_cancelled, 0);
     }
     ctx->branch_taken = NULL;
-    if (pkt->pkt_has_cof) {
+    if (ctx->pkt.pkt_has_cof) {
         ctx->branch_taken = tcg_temp_new();
-        if (pkt->pkt_has_multi_cof) {
+        if (ctx->pkt.pkt_has_multi_cof) {
             tcg_gen_movi_tl(ctx->branch_taken, 0);
         }
         if (need_next_PC(ctx)) {
@@ -503,7 +495,7 @@ static void gen_start_packet(DisasContext *ctx)
      * Preload the predicated pred registers into ctx->new_pred_value[pred_num]
      * Only endloop instructions conditionally write to pred registers
      */
-    if (ctx->need_commit && pkt->pkt_has_endloop) {
+    if (ctx->need_commit && ctx->pkt.pkt_has_endloop) {
         for (i = 0; i < ctx->preg_log_idx; i++) {
             int pred_num = ctx->preg_log[i];
             ctx->new_pred_value[pred_num] = tcg_temp_new();
@@ -542,13 +534,11 @@ static void gen_start_packet(DisasContext *ctx)
 
 bool is_gather_store_insn(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-    Insn *insn = ctx->insn;
-    if (GET_ATTRIB(insn->opcode, A_CVI_NEW) &&
-        insn->new_value_producer_slot == 1) {
+    if (GET_ATTRIB(ctx->insn->opcode, A_CVI_NEW) &&
+        ctx->insn->new_value_producer_slot == 1) {
         /* Look for gather instruction */
-        for (int i = 0; i < pkt->num_insns; i++) {
-            Insn *in = &pkt->insn[i];
+        for (int i = 0; i < ctx->pkt.num_insns; i++) {
+            Insn *in = &ctx->pkt.insn[i];
             if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) {
                 return true;
             }
@@ -651,7 +641,7 @@ static bool slot_is_predicated(Packet *pkt, int slot_num)
 
 void process_store(DisasContext *ctx, int slot_num)
 {
-    bool is_predicated = slot_is_predicated(ctx->pkt, slot_num);
+    bool is_predicated = slot_is_predicated(&ctx->pkt, slot_num);
     TCGLabel *label_end = NULL;
 
     /*
@@ -728,13 +718,12 @@ static void process_store_log(DisasContext *ctx)
      *  slot 1 and then slot 0.  This will be important when
      *  the memory accesses overlap.
      */
-    Packet *pkt = ctx->pkt;
-    if (pkt->pkt_has_scalar_store_s1) {
-        g_assert(!pkt->pkt_has_dczeroa);
+    if (ctx->pkt.pkt_has_scalar_store_s1) {
+        g_assert(!ctx->pkt.pkt_has_dczeroa);
         process_store(ctx, 1);
     }
-    if (pkt->pkt_has_scalar_store_s0) {
-        g_assert(!pkt->pkt_has_dczeroa);
+    if (ctx->pkt.pkt_has_scalar_store_s0) {
+        g_assert(!ctx->pkt.pkt_has_dczeroa);
         process_store(ctx, 0);
     }
 }
@@ -742,7 +731,7 @@ static void process_store_log(DisasContext *ctx)
 /* Zero out a 32-bit cache line */
 static void process_dczeroa(DisasContext *ctx)
 {
-    if (ctx->pkt->pkt_has_dczeroa) {
+    if (ctx->pkt.pkt_has_dczeroa) {
         /* Store 32 bytes of zero starting at (addr & ~0x1f) */
         TCGv addr = tcg_temp_new();
         TCGv_i64 zero = tcg_constant_i64(0);
@@ -776,7 +765,7 @@ static void gen_commit_hvx(DisasContext *ctx)
 
     /* Early exit if not needed */
     if (!ctx->need_commit) {
-        g_assert(!pkt_has_hvx_store(ctx->pkt));
+        g_assert(!pkt_has_hvx_store(&ctx->pkt));
         return;
     }
 
@@ -810,25 +799,23 @@ static void gen_commit_hvx(DisasContext *ctx)
         tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
     }
 
-    if (pkt_has_hvx_store(ctx->pkt)) {
+    if (pkt_has_hvx_store(&ctx->pkt)) {
         gen_helper_commit_hvx_stores(tcg_env);
     }
 }
 
 static void update_exec_counters(DisasContext *ctx)
 {
-    Packet *pkt = ctx->pkt;
-    int num_insns = pkt->num_insns;
     int num_real_insns = 0;
     int num_hvx_insns = 0;
 
-    for (int i = 0; i < num_insns; i++) {
-        if (!pkt->insn[i].is_endloop &&
-            !pkt->insn[i].part1 &&
-            !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) {
+    for (int i = 0; i < ctx->pkt.num_insns; i++) {
+        if (!ctx->pkt.insn[i].is_endloop &&
+            !ctx->pkt.insn[i].part1 &&
+            !GET_ATTRIB(ctx->pkt.insn[i].opcode, A_IT_NOP)) {
             num_real_insns++;
         }
-        if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) {
+        if (GET_ATTRIB(ctx->pkt.insn[i].opcode, A_CVI)) {
             num_hvx_insns++;
         }
     }
@@ -857,12 +844,11 @@ static void gen_commit_packet(DisasContext *ctx)
      * store.  Therefore, we call process_store_log before anything else
      * involved in committing the packet.
      */
-    Packet *pkt = ctx->pkt;
-    bool has_store_s0 = pkt->pkt_has_scalar_store_s0;
+    bool has_store_s0 = ctx->pkt.pkt_has_scalar_store_s0;
     bool has_store_s1 =
-        (pkt->pkt_has_scalar_store_s1 && !ctx->s1_store_processed);
-    bool has_hvx_store = pkt_has_hvx_store(pkt);
-    if (pkt->pkt_has_dczeroa) {
+        (ctx->pkt.pkt_has_scalar_store_s1 && !ctx->s1_store_processed);
+    bool has_hvx_store = pkt_has_hvx_store(&ctx->pkt);
+    if (ctx->pkt.pkt_has_dczeroa) {
         /*
          * The dczeroa will be the store in slot 0, check that we don't have
          * a store in slot 1 or an HVX store.
@@ -889,12 +875,11 @@ static void gen_commit_packet(DisasContext *ctx)
                     FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
                                HAS_HVX_STORES, 1);
             }
-            if (has_store_s0 && slot_is_predicated(pkt, 0)) {
-                mask =
-                    FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
-                               S0_IS_PRED, 1);
+            if (has_store_s0 && slot_is_predicated(&ctx->pkt, 0)) {
+                mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,
+                                  1);
             }
-            if (has_store_s1 && slot_is_predicated(pkt, 1)) {
+            if (has_store_s1 && slot_is_predicated(&ctx->pkt, 1)) {
                 mask =
                     FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
                                S1_IS_PRED, 1);
@@ -912,7 +897,7 @@ static void gen_commit_packet(DisasContext *ctx)
         int args = 0;
         args =
             FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx);
-        if (slot_is_predicated(pkt, 0)) {
+        if (slot_is_predicated(&ctx->pkt, 0)) {
             args =
                 FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
         }
@@ -924,18 +909,18 @@ static void gen_commit_packet(DisasContext *ctx)
 
     gen_reg_writes(ctx);
     gen_pred_writes(ctx);
-    if (pkt->pkt_has_hvx) {
+    if (ctx->pkt.pkt_has_hvx) {
         gen_commit_hvx(ctx);
     }
     update_exec_counters(ctx);
 
-    if (pkt->vhist_insn != NULL) {
+    if (ctx->pkt.vhist_insn != NULL) {
         ctx->pre_commit = false;
-        ctx->insn = pkt->vhist_insn;
-        pkt->vhist_insn->generate(ctx);
+        ctx->insn = ctx->pkt.vhist_insn;
+        ctx->pkt.vhist_insn->generate(ctx);
     }
 
-    if (pkt->pkt_has_cof) {
+    if (ctx->pkt.pkt_has_cof) {
         gen_end_tb(ctx);
     }
 }
@@ -944,7 +929,6 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
 {
     uint32_t words[PACKET_WORDS_MAX];
     int nwords, words_read;
-    Packet pkt;
     int i;
 
     nwords = read_packet_words(env, ctx, words);
@@ -953,22 +937,21 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
         return;
     }
 
-    ctx->pkt = &pkt;
-    words_read = decode_packet(ctx, nwords, words, &pkt, false);
+    words_read = decode_packet(ctx, nwords, words, &ctx->pkt, false);
     if (words_read > 0) {
-        pkt.pc = ctx->base.pc_next;
-        if (pkt.pkt_has_write_conflict) {
+        ctx->pkt.pc = ctx->base.pc_next;
+        if (ctx->pkt.pkt_has_write_conflict) {
             gen_exception_decode_fail(ctx, words_read,
                                       HEX_CAUSE_REG_WRITE_CONFLICT);
             return;
         }
         gen_start_packet(ctx);
-        for (i = 0; i < pkt.num_insns; i++) {
-            ctx->insn = &pkt.insn[i];
+        for (i = 0; i < ctx->pkt.num_insns; i++) {
+            ctx->insn = &ctx->pkt.insn[i];
             gen_insn(ctx);
         }
         gen_commit_packet(ctx);
-        ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
+        ctx->base.pc_next += ctx->pkt.encod_pkt_size_in_bytes;
     } else {
         gen_exception_decode_fail(ctx, nwords, HEX_CAUSE_INVALID_PACKET);
     }
diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py
index 87b7f10d7fd..e7f90a0da11 100755
--- a/target/hexagon/gen_tcg_funcs.py
+++ b/target/hexagon/gen_tcg_funcs.py
@@ -72,7 +72,7 @@ def gen_tcg_func(f, tag, regs, imms):
         for immlett, bits, immshift in imms:
             declared.append(hex_common.imm_name(immlett))
 
-        arguments = ", ".join(["ctx", "ctx->insn", "ctx->pkt"] + declared)
+        arguments = ", ".join(["ctx", "ctx->insn", "&ctx->pkt"] + declared)
         f.write(f"    emit_{tag}({arguments});\n")
 
     elif hex_common.skip_qemu_helper(tag):
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index c0e9f26aebe..e37d5a514f0 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon/hex_common.py
@@ -1144,7 +1144,7 @@ def helper_args(tag, regs, imms):
     if need_pkt_has_multi_cof(tag):
         args.append(HelperArg(
             "i32",
-            "tcg_constant_tl(ctx->pkt->pkt_has_multi_cof)",
+            "tcg_constant_tl(ctx->pkt.pkt_has_multi_cof)",
             "uint32_t pkt_has_multi_cof"
         ))
     if need_pkt_need_commit(tag):
@@ -1156,7 +1156,7 @@ def helper_args(tag, regs, imms):
     if need_PC(tag):
         args.append(HelperArg(
             "i32",
-            "tcg_constant_tl(ctx->pkt->pc)",
+            "tcg_constant_tl(ctx->pkt.pc)",
             "target_ulong PC"
         ))
     if need_next_PC(tag):
-- 
2.34.1

Re: [PULL 0/9] hex queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 116 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PULL 0/9] hex queue

[Brian Cain]

The following changes since commit 667e1fff878326c35c7f5146072e60a63a9a41c8:

  Merge tag 'hw-misc-20251230' of https://github.com/philmd/qemu into staging (2025-12-31 16:44:17 +1100)

are available in the Git repository at:

  https://github.com/quic/qemu tags/pull-hex-20260102

for you to fetch changes up to 15722c774ab2fa6904464cd531bc1120d9553896:

  Hexagon (target/hexagon) s/log_write/gen_write (2025-12-31 22:57:44 -0600)

----------------------------------------------------------------
Bypass packet commit for implicit usr write; cleanup

----------------------------------------------------------------
Taylor Simpson (9):
      Hexagon (target/hexagon) Remove gen_tcg_func_table.py
      Hexagon (target/hexagon) Add pkt_need_commit argument to arch_fpop_end
      Hexagon (target/hexagon) Implicit writes to USR don't force packet commit
      Hexagon (tests/tcg/hexagon) Add test for USR changes in packet
      Hexagon (target/hexagon) analyze all reads before writes
      Hexagon (target/hexagon) Remove gen_log_reg_write
      Hexagon (target/hexagon) s/gen_log_pred_write/gen_pred_write
      Hexagon (target/hexagon) s/gen_log_vreg_write/gen_vreg_write
      Hexagon (target/hexagon) s/log_write/gen_write

 target/hexagon/arch.h                       |   2 +-
 target/hexagon/gen_tcg.h                    | 125 ++++++------
 target/hexagon/genptr.h                     |   3 +-
 target/hexagon/helper.h                     | 114 +++++------
 target/hexagon/translate.h                  |   1 +
 target/hexagon/arch.c                       |   3 +-
 target/hexagon/genptr.c                     |  92 ++++-----
 target/hexagon/idef-parser/parser-helpers.c |   4 +-
 target/hexagon/op_helper.c                  | 287 +++++++++++++++++-----------
 target/hexagon/translate.c                  |  53 +++--
 tests/tcg/hexagon/usr.c                     |  54 ++++++
 target/hexagon/README                       |  11 +-
 target/hexagon/gen_analyze_funcs.py         |   4 +
 target/hexagon/gen_helper_funcs.py          |   8 +-
 target/hexagon/gen_tcg_func_table.py        |  66 -------
 target/hexagon/gen_tcg_funcs.py             |   7 +-
 target/hexagon/hex_common.py                |  56 +++---
 target/hexagon/meson.build                  |  10 -
 18 files changed, 472 insertions(+), 428 deletions(-)
 delete mode 100755 target/hexagon/gen_tcg_func_table.py

Re: [PULL 0/9] hex queue

[Richard Henderson]

On 1/3/26 07:11, Brian Cain wrote:
> The following changes since commit 667e1fff878326c35c7f5146072e60a63a9a41c8:
> 
>    Merge tag 'hw-misc-20251230' ofhttps://github.com/philmd/qemu into staging (2025-12-31 16:44:17 +1100)
> 
> are available in the Git repository at:
> 
>    https://github.com/quic/qemu tags/pull-hex-20260102
> 
> for you to fetch changes up to 15722c774ab2fa6904464cd531bc1120d9553896:
> 
>    Hexagon (target/hexagon) s/log_write/gen_write (2025-12-31 22:57:44 -0600)
> 
> ----------------------------------------------------------------
> Bypass packet commit for implicit usr write; cleanup


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/11.0 as appropriate.

r~