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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/28] hvf: arm: physical timer emulation
Date: Fri,  1 May 2026 11:15:03 +0100	[thread overview]
Message-ID: <20260501101505.3485916-27-peter.maydell@linaro.org> (raw)
In-Reply-To: <20260501101505.3485916-1-peter.maydell@linaro.org>

From: Mohamed Mediouni <mohamed@unpredictable.fr>

Enable this through leveraging TCG's physical timer emulation.
This allows nested virtualisation to work with a kernel-irqchip=off + GICv2.

Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Message-id: 20260429190532.26538-14-mohamed@unpredictable.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/hvf/hvf.c | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 6062e08c49..2252b96f83 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -189,7 +189,9 @@ void hvf_arm_init_debug(void)
 #define SYSREG_OSDLR_EL1      SYSREG(2, 0, 1, 3, 4)
 #define SYSREG_LORC_EL1       SYSREG(3, 0, 10, 4, 3)
 #define SYSREG_CNTPCT_EL0     SYSREG(3, 3, 14, 0, 1)
+#define SYSREG_CNTP_TVAL_EL0   SYSREG(3, 3, 14, 2, 0)
 #define SYSREG_CNTP_CTL_EL0   SYSREG(3, 3, 14, 2, 1)
+#define SYSREG_CNTP_CVAL_EL0   SYSREG(3, 3, 14, 2, 2)
 #define SYSREG_PMCR_EL0       SYSREG(3, 3, 9, 12, 0)
 #define SYSREG_PMUSERENR_EL0  SYSREG(3, 3, 9, 14, 0)
 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
@@ -1719,9 +1721,15 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
 
     switch (reg) {
     case SYSREG_CNTPCT_EL0:
-        *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
-              gt_cntfrq_period_ns(arm_cpu);
-        return 0;
+    case SYSREG_CNTP_CTL_EL0:
+    case SYSREG_CNTP_CVAL_EL0:
+    case SYSREG_CNTP_TVAL_EL0:
+        assert(!hvf_irqchip_in_kernel());
+        /* Call the TCG sysreg handler. */
+        if (hvf_sysreg_read_cp(cpu, "PTimer", reg, val)) {
+            return 0;
+        }
+        break;
     case SYSREG_OSLSR_EL1:
         *val = env->cp15.oslsr_el1;
         return 0;
@@ -2015,12 +2023,14 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
         env->cp15.oslsr_el1 = val & 1;
         return 0;
     case SYSREG_CNTP_CTL_EL0:
-        /*
-         * Guests should not rely on the physical counter, but macOS emits
-         * disable writes to it. Let it do so, but ignore the requests.
-         */
-        qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n");
-        return 0;
+    case SYSREG_CNTP_CVAL_EL0:
+    case SYSREG_CNTP_TVAL_EL0:
+        assert(!hvf_irqchip_in_kernel());
+        /* Call the TCG sysreg handler. */
+        if (hvf_sysreg_write_cp(cpu, "PTimer", reg, val)) {
+            return 0;
+        }
+        break;
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         return 0;
-- 
2.43.0



  parent reply	other threads:[~2026-05-01 10:17 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-01 10:14 [PULL 00/28] target-arm queue Peter Maydell
2026-05-01 10:14 ` [PULL 01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices Peter Maydell
2026-05-01 10:14 ` [PULL 02/28] hw/arm/fsl-imx8mp: Fix parent of ocram memory region Peter Maydell
2026-05-01 10:14 ` [PULL 03/28] Revert "sysbus: add irq_routing_notifier" Peter Maydell
2026-05-01 10:14 ` [PULL 04/28] linux-user/arm: Restrict regpairs_aligned Peter Maydell
2026-05-01 10:14 ` [PULL 05/28] qemu-options: Improve description for -smb option Peter Maydell
2026-05-01 10:14 ` [PULL 06/28] target/arm/cpu-features.c: New fields in AA64MMFR4 Peter Maydell
2026-05-01 10:14 ` [PULL 07/28] target/arm/cpu.h: New GPCCR fields Peter Maydell
2026-05-01 10:14 ` [PULL 08/28] target/arm/ptw.c: Add GDI spaces to the granule protection case Peter Maydell
2026-05-01 10:14 ` [PULL 09/28] tests/tcg/aarch64/system/rme_gdi.c: Very basic test of GDI Peter Maydell
2026-05-01 10:14 ` [PULL 10/28] docs/devel/decodetree: Fix formatting in "field examples" table Peter Maydell
2026-05-01 10:14 ` [PULL 11/28] hw/net/allwinner-sun8i-emac: Flush queued packets when rx is enabled Peter Maydell
2026-05-01 10:14 ` [PULL 12/28] hw/intc/arm_gicv3: Fix NS write to ICC_AP1Rn_EL1 when prebits < 7 Peter Maydell
2026-05-01 10:14 ` [PULL 13/28] target/arm/kvm: Cache host CPU probe failure Peter Maydell
2026-05-01 10:14 ` [PULL 14/28] hw/intc: Add hvf vGIC interrupt controller support Peter Maydell
2026-05-01 10:14 ` [PULL 15/28] hw/intc: arm_gicv3_hvf: save/restore Apple GIC state Peter Maydell
2026-05-07  8:08   ` Philippe Mathieu-Daudé
2026-06-13 11:45   ` Philippe Mathieu-Daudé
2026-06-13 11:49     ` Mohamed Mediouni
2026-05-01 10:14 ` [PULL 16/28] accel, hw/arm, include/system/hvf: infrastructure changes for HVF vGIC Peter Maydell
2026-05-01 10:14 ` [PULL 17/28] target/arm: hvf: instantiate GIC early Peter Maydell
2026-05-01 10:14 ` [PULL 18/28] hw/arm, target/arm: nested virtualisation on HVF Peter Maydell
2026-05-01 10:14 ` [PULL 19/28] hvf: only call hvf_sync_vtimer() when running without the platform vGIC Peter Maydell
2026-05-01 10:14 ` [PULL 20/28] hvf: gate ARM_FEATURE_PMU register emulation when using the Apple vGIC Peter Maydell
2026-05-01 10:14 ` [PULL 21/28] hvf: arm: allow exposing minimal PMU for kernel-irqchip=on Peter Maydell
2026-05-01 10:14 ` [PULL 22/28] target/arm: hvf: add asserts for code paths not leveraged when using the vGIC Peter Maydell
2026-05-01 10:15 ` [PULL 23/28] hvf: sync registers used at EL2 Peter Maydell
2026-05-01 10:59   ` Stefan Hajnoczi
2026-05-01 23:20     ` Mohamed Mediouni
2026-05-01 10:15 ` [PULL 24/28] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1 Peter Maydell
2026-05-01 10:15 ` [PULL 25/28] hvf: arm: disable SME when nested virt is active Peter Maydell
2026-05-01 10:15 ` Peter Maydell [this message]
2026-05-01 10:15 ` [PULL 27/28] hvf: enable nested virtualisation support Peter Maydell
2026-05-01 10:15 ` [PULL 28/28] hvf: arm: enable vGIC by default for virt-11.1 and later Peter Maydell

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