[PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine

[Nicholas Piggin <npiggin@gmail.com>]

Introducing Tenstorrent Atlantis!

 The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
 and CoreLab Technology. It is based on the Atlantis SoC, which includes
 the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.

 The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
 RISC-V CPU.

I will taking over this series while Joel is away. Many thanks to the
reviewers on v4, here:

https://lore.kernel.org/qemu-devel/20260425131721.932250-1-joel@jms.id.au/T/#mb1ef2824c2f1f37bf4574dc1ef0fb95566c3a2f2

Changes since v4:
- Drop PCI, to rewok with Designware controller in a later patch.
- Drop I2C, the model had significant changes so I will work on
  that independently and we can bring that back in Atlantis later.
- Move the OpenSBI dummy payload hack into tt-atlantis specific code.
- Remove AIA MAINTAINERS entry since it is already covered.
- Update microchip_pfsoc to use new discontig boot_info API.
- Update changelog to explain tt-atlantis machine DTB.

Thanks,
Nick

Joel Stanley (3):
  hw/riscv/virt: Move AIA initialisation to helper file
  hw/riscv/aia: Provide number of irq sources
  hw/riscv: Add Tenstorrent Atlantis machine

Nicholas Piggin (6):
  hw/riscv/boot: Describe discontiguous memory in boot_info
  hw/riscv/boot: Account for discontiguous memory when loading firmware
  target/riscv: tt-ascalon: Enable Zkr extension
  target/riscv: tt-ascalon: Enable Svadu by removing Svade
  hw/riscv/atlantis: Provide a simple halting payload
  tests/functional/riscv64: Add tt-atlantis tests

 MAINTAINERS                                  |  11 +
 docs/system/riscv/tt_atlantis.rst            |  32 +
 docs/system/target-riscv.rst                 |   1 +
 hw/riscv/Kconfig                             |  10 +
 hw/riscv/aia.c                               |  93 +++
 hw/riscv/aia.h                               |  25 +
 hw/riscv/boot.c                              |  34 +-
 hw/riscv/meson.build                         |   3 +-
 hw/riscv/microchip_pfsoc.c                   |   8 +-
 hw/riscv/opentitan.c                         |   6 +-
 hw/riscv/shakti_c.c                          |   6 +-
 hw/riscv/sifive_u.c                          |   6 +-
 hw/riscv/spike.c                             |   6 +-
 hw/riscv/tt_atlantis.c                       | 583 +++++++++++++++++++
 hw/riscv/virt-acpi-build.c                   |  27 +-
 hw/riscv/virt.c                              |  96 +--
 hw/riscv/xiangshan_kmh.c                     |   6 +-
 include/hw/riscv/boot.h                      |  12 +-
 include/hw/riscv/tt_atlantis.h               |  51 ++
 include/hw/riscv/virt.h                      |   2 +-
 roms/seabios-hppa                            |   2 +-
 target/riscv/cpu.c                           |   2 +-
 tests/functional/riscv64/meson.build         |   1 +
 tests/functional/riscv64/test_opensbi.py     |   4 +
 tests/functional/riscv64/test_tt_atlantis.py |  57 ++
 25 files changed, 975 insertions(+), 109 deletions(-)
 create mode 100644 docs/system/riscv/tt_atlantis.rst
 create mode 100644 hw/riscv/aia.c
 create mode 100644 hw/riscv/aia.h
 create mode 100644 hw/riscv/tt_atlantis.c
 create mode 100644 include/hw/riscv/tt_atlantis.h
 create mode 100755 tests/functional/riscv64/test_tt_atlantis.py

-- 
2.53.0