From: Nicholas Piggin <npiggin@gmail.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Chao Liu <chao.liu.zevorn@gmail.com>,
Michael Ellerman <mpe@kernel.org>,
Joel Stanley <jms@oss.tenstorrent.com>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Portia Stephens <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Joel Stanley <joel@jms.id.au>
Subject: Re: [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade
Date: Fri, 8 May 2026 13:54:30 +1000 [thread overview]
Message-ID: <af1UmCFaLRERlpwa@lima-default> (raw)
In-Reply-To: <dic5owmgvmaoqhiinu3v6kcdyakwt6kj4ryfw5vm446w3pv6mj@77kcjokjpnem>
On Thu, May 07, 2026 at 01:57:02PM -0500, Andrew Jones wrote:
> On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote:
> > Ascalon supports Svadu (hardware A/D bit updates).
> >
> > QEMU makes Svadu and Svade mutually exclusive, remove Svade so
> > Ascalon comes up with Svadu working.
>
> Hi Nicholas,
>
> Svadu and Svade aren't mutually exclusive, you can see the expected
> behaviors for the pair in the commit message of commit 70d22fd92c3b
> ("target/riscv: Gate hardware A/D PTE bit updating").
Okay misunderstood what QEMU is doing. What does it mean for an
implementation to support Svadu && !Svade? AFAIKS the spec says ADUE=0
means the access is performed as though Svade is implemented. I'm either
wrong about that or miss the point why Svadu && Svade is handled
differently in the patch you reference (or both).
> Does the
> Ascalon support Svade? If so, then it's probably best to enable both
> and leave it to Linux to enable Svadu with SBI FWFT
> SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of
> software supported. But, unfortunately Linux doesn't yet support the
> checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still
> need kernel patches for that.
Our docs say it supports both. If enabling both bits is the correct
thing to do we should go with that for upstream.
Thanks,
Nick
next prev parent reply other threads:[~2026-05-08 3:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 1/9] hw/riscv/boot: Describe discontiguous memory in boot_info Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 2/9] hw/riscv/boot: Account for discontiguous memory when loading firmware Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 3/9] hw/riscv/virt: Move AIA initialisation to helper file Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 4/9] hw/riscv/aia: Provide number of irq sources Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 5/9] target/riscv: tt-ascalon: Enable Zkr extension Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade Nicholas Piggin
2026-05-07 18:57 ` Andrew Jones
2026-05-08 3:54 ` Nicholas Piggin [this message]
2026-05-08 13:56 ` Andrew Jones
2026-05-07 4:38 ` [PATCH v5 7/9] hw/riscv: Add Tenstorrent Atlantis machine Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload Nicholas Piggin
2026-05-07 6:09 ` Philippe Mathieu-Daudé
2026-05-07 4:38 ` [PATCH v5 9/9] tests/functional/riscv64: Add tt-atlantis tests Nicholas Piggin
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