* [PATCH v5 1/9] hw/riscv/boot: Describe discontiguous memory in boot_info
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 2/9] hw/riscv/boot: Account for discontiguous memory when loading firmware Nicholas Piggin
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley
Machines that have discontiguous memory may need to adjust where
firmware and images are loaded at boot. Provide an interface for
machines to describe a discontiguous low/high RAM scheme for this
purpose.
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/riscv/boot.c | 16 ++++++++++++++++
include/hw/riscv/boot.h | 7 +++++++
roms/seabios-hppa | 2 +-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 9086793b7a..6e0c6c2d17 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -69,11 +69,27 @@ char *riscv_plic_hart_config_string(int hart_count)
void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
{
+ info->ram_low_start = 0;
+ info->ram_low_size = 0;
info->kernel_size = 0;
info->initrd_size = 0;
info->is_32bit = riscv_is_32bit(harts);
}
+/*
+ * This can be used instead of riscv_boot_info_init() if the machine has
+ * discontiguous physical memory. The low memory range specified will be
+ * used to place firmware images.
+ */
+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,
+ RISCVHartArrayState *harts,
+ hwaddr low_start, hwaddr low_size)
+{
+ riscv_boot_info_init(info, harts);
+ info->ram_low_start = low_start;
+ info->ram_low_size = low_size;
+}
+
vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
hwaddr firmware_end_addr) {
if (info->is_32bit) {
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f00b3ca122..69c99a1496 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -28,6 +28,10 @@
#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
typedef struct RISCVBootInfo {
+ /* First contiguous RAM region. If size is zero then assume entire RAM */
+ hwaddr ram_low_start;
+ hwaddr ram_low_size;
+
ssize_t kernel_size;
hwaddr image_low_addr;
hwaddr image_high_addr;
@@ -43,6 +47,9 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);
char *riscv_plic_hart_config_string(int hart_count);
void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
+void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,
+ RISCVHartArrayState *harts,
+ hwaddr low_start, hwaddr low_size);
vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
hwaddr firmware_end_addr);
hwaddr riscv_find_and_load_firmware(MachineState *machine,
diff --git a/roms/seabios-hppa b/roms/seabios-hppa
index d9560852a3..1a8ada1fb7 160000
--- a/roms/seabios-hppa
+++ b/roms/seabios-hppa
@@ -1 +1 @@
-Subproject commit d9560852a34f156155b3777745baa0d96d553f22
+Subproject commit 1a8ada1fb70643172e251aacbac673c9ecda99e9
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 2/9] hw/riscv/boot: Account for discontiguous memory when loading firmware
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 1/9] hw/riscv/boot: Describe discontiguous memory in boot_info Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 3/9] hw/riscv/virt: Move AIA initialisation to helper file Nicholas Piggin
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley
This loads firmware into the first (low) memory range,
accounting for machines having discontiguous memory regions.
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/riscv/boot.c | 18 ++++++++++++------
hw/riscv/microchip_pfsoc.c | 8 ++++++--
hw/riscv/opentitan.c | 6 ++++--
hw/riscv/shakti_c.c | 6 +++++-
hw/riscv/sifive_u.c | 6 ++++--
hw/riscv/spike.c | 6 ++++--
hw/riscv/virt.c | 7 ++++---
hw/riscv/xiangshan_kmh.c | 6 +++++-
include/hw/riscv/boot.h | 5 ++++-
9 files changed, 48 insertions(+), 20 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 6e0c6c2d17..2b1f11ea15 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -150,6 +150,7 @@ char *riscv_find_firmware(const char *firmware_filename,
}
hwaddr riscv_find_and_load_firmware(MachineState *machine,
+ RISCVBootInfo *info,
const char *default_machine_firmware,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb)
@@ -162,7 +163,8 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,
if (firmware_filename) {
/* If not "none" load the firmware */
- firmware_end_addr = riscv_load_firmware(firmware_filename,
+ firmware_end_addr = riscv_load_firmware(machine, info,
+ firmware_filename,
firmware_load_addr, sym_cb);
g_free(firmware_filename);
}
@@ -170,10 +172,13 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,
return firmware_end_addr;
}
-hwaddr riscv_load_firmware(const char *firmware_filename,
+hwaddr riscv_load_firmware(MachineState *machine,
+ const RISCVBootInfo *info,
+ const char *firmware_filename,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb)
{
+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
uint64_t firmware_entry, firmware_end;
ssize_t firmware_size;
@@ -202,7 +207,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
firmware_size = load_image_targphys_as(firmware_filename,
*firmware_load_addr,
- current_machine->ram_size, NULL,
+ mem_size, NULL,
NULL);
if (firmware_size > 0) {
@@ -217,7 +222,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
{
const char *filename = machine->initrd_filename;
- uint64_t mem_size = machine->ram_size;
+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
void *fdt = machine->fdt;
hwaddr start, end;
ssize_t size;
@@ -263,6 +268,7 @@ void riscv_load_kernel(MachineState *machine,
bool load_initrd,
symbol_fn_t sym_cb)
{
+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
ssize_t kernel_size;
void *fdt = machine->fdt;
@@ -294,7 +300,7 @@ void riscv_load_kernel(MachineState *machine,
}
kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
- current_machine->ram_size, NULL, NULL);
+ mem_size, NULL, NULL);
if (kernel_size > 0) {
info->kernel_size = kernel_size;
info->image_low_addr = kernel_start_addr;
@@ -390,7 +396,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
- error_report("No enough memory to place DTB after kernel/initrd");
+ error_report("Not enough memory to place DTB after kernel/initrd");
exit(1);
}
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 743f31f005..60bb96da01 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -618,18 +618,22 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
firmware_load_addr = RESET_VECTOR;
}
+ riscv_boot_info_init_discontig_mem(&boot_info, &s->soc.u_cpus,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ mem_low_size);
+
/* Load the firmware if necessary */
firmware_end_addr = firmware_load_addr;
if (firmware_name) {
char *filename = riscv_find_firmware(firmware_name, NULL);
if (filename) {
- firmware_end_addr = riscv_load_firmware(filename,
+ firmware_end_addr = riscv_load_firmware(machine, &boot_info,
+ filename,
&firmware_load_addr, NULL);
g_free(filename);
}
}
- riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 309125e854..8cd660dd41 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -99,12 +99,14 @@ static void opentitan_machine_init(MachineState *machine)
memory_region_add_subregion(sys_mem,
memmap[IBEX_DEV_RAM].base, machine->ram);
+ riscv_boot_info_init(&boot_info, &s->soc.cpus);
+
if (machine->firmware) {
hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;
- riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
+ riscv_load_firmware(machine, &boot_info, machine->firmware,
+ &firmware_load_addr, NULL);
}
- riscv_boot_info_init(&boot_info, &s->soc.cpus);
if (machine->kernel_filename) {
riscv_load_kernel(machine, &boot_info,
memmap[IBEX_DEV_RAM].base,
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 49a39b3021..eb720d9cdf 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -45,6 +45,7 @@ static void shakti_c_machine_state_init(MachineState *mstate)
{
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
+ RISCVBootInfo boot_info;
hwaddr firmware_load_addr = shakti_c_memmap[SHAKTI_C_RAM].base;
/* Initialize SoC */
@@ -57,8 +58,11 @@ static void shakti_c_machine_state_init(MachineState *mstate)
shakti_c_memmap[SHAKTI_C_RAM].base,
mstate->ram);
+ riscv_boot_info_init(&boot_info, &sms->soc.cpus);
+
if (mstate->firmware) {
- riscv_load_firmware(mstate->firmware, &firmware_load_addr, NULL);
+ riscv_load_firmware(mstate, &boot_info, mstate->firmware,
+ &firmware_load_addr, NULL);
}
/* ROM reset vector */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 7ec67b2565..dda8687bfd 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -589,11 +589,13 @@ static void sifive_u_machine_init(MachineState *machine)
break;
}
+ riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
+
firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
- firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info,
+ firmware_name,
&start_addr, NULL);
- riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 35c696f891..6ee915a8ba 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -281,9 +281,12 @@ static void spike_board_init(MachineState *machine)
}
}
+ riscv_boot_info_init(&boot_info, &s->soc[0]);
+
/* Load firmware */
if (firmware_name) {
- firmware_end_addr = riscv_load_firmware(firmware_name,
+ firmware_end_addr = riscv_load_firmware(machine, &boot_info,
+ firmware_name,
&firmware_load_addr,
htif_symbol_callback);
g_free(firmware_name);
@@ -293,7 +296,6 @@ static void spike_board_init(MachineState *machine)
create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
/* Load kernel */
- riscv_boot_info_init(&boot_info, &s->soc[0]);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a1c323e66d..4501d5581b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1457,7 +1457,10 @@ static void virt_machine_done(Notifier *notifier, void *data)
}
}
- firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ riscv_boot_info_init(&boot_info, &s->soc[0]);
+
+ firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info,
+ firmware_name,
&start_addr, NULL);
pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
@@ -1480,8 +1483,6 @@ static void virt_machine_done(Notifier *notifier, void *data)
}
}
- riscv_boot_info_init(&boot_info, &s->soc[0]);
-
if (machine->kernel_filename && !kernel_entry) {
kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
firmware_end_addr);
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 436e51c1c5..247a0b5d1f 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -166,6 +166,7 @@ static void xiangshan_kmh_machine_init(MachineState *machine)
const MemMapEntry *memmap = xiangshan_kmh_memmap;
MemoryRegion *system_memory = get_system_memory();
hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;
+ RISCVBootInfo boot_info;
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
@@ -177,13 +178,16 @@ static void xiangshan_kmh_machine_init(MachineState *machine)
memmap[XIANGSHAN_KMH_DRAM].base,
machine->ram);
+ riscv_boot_info_init(&boot_info, &s->soc.cpus);
+
/* ROM reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc.cpus,
start_addr,
memmap[XIANGSHAN_KMH_ROM].base,
memmap[XIANGSHAN_KMH_ROM].size, 0, 0);
if (machine->firmware) {
- riscv_load_firmware(machine->firmware, &start_addr, NULL);
+ riscv_load_firmware(machine, &boot_info, machine->firmware,
+ &start_addr, NULL);
}
/* Note: dtb has been integrated into firmware(OpenSBI) when compiling */
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 69c99a1496..4e7bd9a225 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,
vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
hwaddr firmware_end_addr);
hwaddr riscv_find_and_load_firmware(MachineState *machine,
+ RISCVBootInfo *info,
const char *default_machine_firmware,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
char *riscv_find_firmware(const char *firmware_filename,
const char *default_machine_firmware);
-hwaddr riscv_load_firmware(const char *firmware_filename,
+hwaddr riscv_load_firmware(MachineState *machine,
+ const RISCVBootInfo *info,
+ const char *firmware_filename,
hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
void riscv_load_kernel(MachineState *machine,
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 3/9] hw/riscv/virt: Move AIA initialisation to helper file
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 1/9] hw/riscv/boot: Describe discontiguous memory in boot_info Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 2/9] hw/riscv/boot: Account for discontiguous memory when loading firmware Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 4/9] hw/riscv/aia: Provide number of irq sources Nicholas Piggin
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley, Nutty Liu, Philippe Mathieu-Daudé
From: Joel Stanley <joel@jms.id.au>
The AIA init will be used by any server class riscv machine. Separate it
out in order to share code with such systems.
The virt machine keeps machine specific #defines such as
VIRT_IRQCHIP_NUM_MSIS, VIRT_IRQCHIP_NUM_PRIO_BITS.
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/riscv/aia.c | 89 ++++++++++++++++++++++++++++++++++++++
hw/riscv/aia.h | 26 +++++++++++
hw/riscv/meson.build | 2 +-
hw/riscv/virt-acpi-build.c | 2 +
hw/riscv/virt.c | 87 +++++--------------------------------
include/hw/riscv/virt.h | 1 -
6 files changed, 129 insertions(+), 78 deletions(-)
create mode 100644 hw/riscv/aia.c
create mode 100644 hw/riscv/aia.h
diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c
new file mode 100644
index 0000000000..c724612a50
--- /dev/null
+++ b/hw/riscv/aia.c
@@ -0,0 +1,89 @@
+/*
+ * QEMU RISC-V Advanced Interrupt Architecture (AIA)
+ *
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "system/kvm.h"
+#include "hw/intc/riscv_aplic.h"
+#include "hw/intc/riscv_imsic.h"
+
+#include "aia.h"
+
+uint32_t imsic_num_bits(uint32_t count)
+{
+ uint32_t ret = 0;
+
+ while (BIT(ret) < count) {
+ ret++;
+ }
+
+ return ret;
+}
+
+DeviceState *riscv_create_aia(bool msimode, int aia_guests,
+ const MemMapEntry *aplic_m,
+ const MemMapEntry *aplic_s,
+ const MemMapEntry *imsic_m,
+ const MemMapEntry *imsic_s,
+ int socket, int base_hartid, int hart_count,
+ uint32_t num_msis, uint32_t num_prio_bits)
+{
+ int i;
+ hwaddr addr = 0;
+ uint32_t guest_bits;
+ DeviceState *aplic_s_dev = NULL;
+ DeviceState *aplic_m_dev = NULL;
+
+ if (msimode) {
+ if (!kvm_enabled()) {
+ /* Per-socket M-level IMSICs */
+ addr = imsic_m->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIFT);
+ for (i = 0; i < hart_count; i++) {
+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
+ base_hartid + i, true, 1,
+ num_msis);
+ }
+ }
+
+ /* Per-socket S-level IMSICs */
+ guest_bits = imsic_num_bits(aia_guests + 1);
+ addr = imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIFT);
+ for (i = 0; i < hart_count; i++) {
+ riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
+ base_hartid + i, false, 1 + aia_guests,
+ num_msis);
+ }
+ }
+
+ if (!kvm_enabled()) {
+ /* Per-socket M-level APLIC */
+ aplic_m_dev = riscv_aplic_create(aplic_m->base +
+ socket * aplic_m->size,
+ aplic_m->size,
+ (msimode) ? 0 : base_hartid,
+ (msimode) ? 0 : hart_count,
+ VIRT_IRQCHIP_NUM_SOURCES,
+ num_prio_bits,
+ msimode, true, NULL);
+ }
+
+ /* Per-socket S-level APLIC */
+ aplic_s_dev = riscv_aplic_create(aplic_s->base +
+ socket * aplic_s->size,
+ aplic_s->size,
+ (msimode) ? 0 : base_hartid,
+ (msimode) ? 0 : hart_count,
+ VIRT_IRQCHIP_NUM_SOURCES,
+ num_prio_bits,
+ msimode, false, aplic_m_dev);
+
+ if (kvm_enabled() && msimode) {
+ riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s_dev), addr);
+ }
+
+ return kvm_enabled() ? aplic_s_dev : aplic_m_dev;
+}
diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h
new file mode 100644
index 0000000000..dbb8333402
--- /dev/null
+++ b/hw/riscv/aia.h
@@ -0,0 +1,26 @@
+/*
+ * QEMU RISC-V Advanced Interrupt Architecture (AIA)
+ *
+ * Copyright (C) 2019 Western Digital Corporation or its affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_RISCV_AIA_H
+#define HW_RISCV_AIA_H
+
+#include "exec/hwaddr.h"
+
+#define VIRT_IRQCHIP_NUM_SOURCES 96
+
+uint32_t imsic_num_bits(uint32_t count);
+
+DeviceState *riscv_create_aia(bool msimode, int aia_guests,
+ const MemMapEntry *aplic_m,
+ const MemMapEntry *aplic_s,
+ const MemMapEntry *imsic_m,
+ const MemMapEntry *imsic_s,
+ int socket, int base_hartid, int hart_count,
+ uint32_t num_msis, uint32_t num_prio_bits);
+
+#endif
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 533472e22a..e53c180d0d 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -1,5 +1,5 @@
riscv_ss = ss.source_set()
-riscv_ss.add(files('boot.c'))
+riscv_ss.add(files('boot.c', 'aia.c'))
riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index fd6ca5dbc4..145f8d92ad 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -42,6 +42,8 @@
#include "system/kvm.h"
#include "system/reset.h"
+#include "aia.h"
+
#define ACPI_BUILD_TABLE_SIZE 0x20000
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4501d5581b..ce0fd6f50c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -59,6 +59,8 @@
#include "hw/virtio/virtio-iommu.h"
#include "hw/uefi/var-service-api.h"
+#include "aia.h"
+
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
{
@@ -509,17 +511,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
}
}
-uint32_t imsic_num_bits(uint32_t count)
-{
- uint32_t ret = 0;
-
- while (BIT(ret) < count) {
- ret++;
- }
-
- return ret;
-}
-
static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr,
uint32_t *intc_phandles, uint32_t msi_phandle,
bool m_mode, uint32_t imsic_guest_bits)
@@ -1293,68 +1284,6 @@ static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
memmap[VIRT_PLIC].size);
}
-static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
- const MemMapEntry *memmap, int socket,
- int base_hartid, int hart_count)
-{
- int i;
- hwaddr addr = 0;
- uint32_t guest_bits;
- DeviceState *aplic_s = NULL;
- DeviceState *aplic_m = NULL;
- bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
-
- if (msimode) {
- if (!kvm_enabled()) {
- /* Per-socket M-level IMSICs */
- addr = memmap[VIRT_IMSIC_M].base +
- socket * VIRT_IMSIC_GROUP_MAX_SIZE;
- for (i = 0; i < hart_count; i++) {
- riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
- base_hartid + i, true, 1,
- VIRT_IRQCHIP_NUM_MSIS);
- }
- }
-
- /* Per-socket S-level IMSICs */
- guest_bits = imsic_num_bits(aia_guests + 1);
- addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
- for (i = 0; i < hart_count; i++) {
- riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
- base_hartid + i, false, 1 + aia_guests,
- VIRT_IRQCHIP_NUM_MSIS);
- }
- }
-
- if (!kvm_enabled()) {
- /* Per-socket M-level APLIC */
- aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base +
- socket * memmap[VIRT_APLIC_M].size,
- memmap[VIRT_APLIC_M].size,
- (msimode) ? 0 : base_hartid,
- (msimode) ? 0 : hart_count,
- VIRT_IRQCHIP_NUM_SOURCES,
- VIRT_IRQCHIP_NUM_PRIO_BITS,
- msimode, true, NULL);
- }
-
- /* Per-socket S-level APLIC */
- aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base +
- socket * memmap[VIRT_APLIC_S].size,
- memmap[VIRT_APLIC_S].size,
- (msimode) ? 0 : base_hartid,
- (msimode) ? 0 : hart_count,
- VIRT_IRQCHIP_NUM_SOURCES,
- VIRT_IRQCHIP_NUM_PRIO_BITS,
- msimode, false, aplic_m);
-
- if (kvm_enabled() && msimode) {
- riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
- }
-
- return kvm_enabled() ? aplic_s : aplic_m;
-}
-
static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
{
DeviceState *dev;
@@ -1617,9 +1546,15 @@ static void virt_machine_init(MachineState *machine)
s->irqchip[i] = virt_create_plic(s->memmap, i,
base_hartid, hart_count);
} else {
- s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
- s->memmap, i, base_hartid,
- hart_count);
+ s->irqchip[i] = riscv_create_aia(s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC,
+ s->aia_guests,
+ &s->memmap[VIRT_APLIC_M],
+ &s->memmap[VIRT_APLIC_S],
+ &s->memmap[VIRT_IMSIC_M],
+ &s->memmap[VIRT_IMSIC_S],
+ i, base_hartid, hart_count,
+ VIRT_IRQCHIP_NUM_MSIS,
+ VIRT_IRQCHIP_NUM_PRIO_BITS);
}
/* Try to use different IRQCHIP instance based device type */
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 18a2a323a3..ad858deb76 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -135,7 +135,6 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
-uint32_t imsic_num_bits(uint32_t count);
/*
* The virt machine physical address space used by some of the devices
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 4/9] hw/riscv/aia: Provide number of irq sources
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (2 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 3/9] hw/riscv/virt: Move AIA initialisation to helper file Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 5/9] target/riscv: tt-ascalon: Enable Zkr extension Nicholas Piggin
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley, Nutty Liu, Philippe Mathieu-Daudé
From: Joel Stanley <joel@jms.id.au>
Instead of hard coding the number of IRQ sources used by the APLIC pass
it in as a parameter. This allows other machines to configure this as
required.
The maximum number of sources is 1023.
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/riscv/aia.c | 8 ++++++--
hw/riscv/aia.h | 3 +--
hw/riscv/virt-acpi-build.c | 25 ++++++++++++++++---------
hw/riscv/virt.c | 2 ++
include/hw/riscv/virt.h | 1 +
5 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c
index c724612a50..82ea9d48ea 100644
--- a/hw/riscv/aia.c
+++ b/hw/riscv/aia.c
@@ -25,6 +25,7 @@ uint32_t imsic_num_bits(uint32_t count)
}
DeviceState *riscv_create_aia(bool msimode, int aia_guests,
+ uint16_t num_sources,
const MemMapEntry *aplic_m,
const MemMapEntry *aplic_s,
const MemMapEntry *imsic_m,
@@ -38,6 +39,9 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,
DeviceState *aplic_s_dev = NULL;
DeviceState *aplic_m_dev = NULL;
+ /* The RISC-V Advanced Interrupt Architecture, Chapter 1.2. Limits */
+ g_assert(num_sources <= 1023);
+
if (msimode) {
if (!kvm_enabled()) {
/* Per-socket M-level IMSICs */
@@ -66,7 +70,7 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,
aplic_m->size,
(msimode) ? 0 : base_hartid,
(msimode) ? 0 : hart_count,
- VIRT_IRQCHIP_NUM_SOURCES,
+ num_sources,
num_prio_bits,
msimode, true, NULL);
}
@@ -77,7 +81,7 @@ DeviceState *riscv_create_aia(bool msimode, int aia_guests,
aplic_s->size,
(msimode) ? 0 : base_hartid,
(msimode) ? 0 : hart_count,
- VIRT_IRQCHIP_NUM_SOURCES,
+ num_sources,
num_prio_bits,
msimode, false, aplic_m_dev);
diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h
index dbb8333402..5ad0a902be 100644
--- a/hw/riscv/aia.h
+++ b/hw/riscv/aia.h
@@ -11,11 +11,10 @@
#include "exec/hwaddr.h"
-#define VIRT_IRQCHIP_NUM_SOURCES 96
-
uint32_t imsic_num_bits(uint32_t count);
DeviceState *riscv_create_aia(bool msimode, int aia_guests,
+ uint16_t num_sources,
const MemMapEntry *aplic_m,
const MemMapEntry *aplic_s,
const MemMapEntry *imsic_m,
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 145f8d92ad..9ef3ef842a 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -146,6 +146,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
+ uint16_t num_sources,
uint64_t mmio_base, uint64_t mmio_size,
const char *hid)
{
@@ -153,9 +154,12 @@ static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count,
uint32_t gsi_base;
uint8_t socket;
+ /* The RISC-V Advanced Interrupt Architecture, Chapter 1.2. Limits */
+ g_assert(num_sources <= 1023);
+
for (socket = 0; socket < socket_count; socket++) {
plic_aplic_addr = mmio_base + mmio_size * socket;
- gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ gsi_base = num_sources * socket;
Aml *dev = aml_device("IC%.02X", socket);
aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid)));
aml_append(dev, aml_name_decl("_UID", aml_int(socket)));
@@ -474,10 +478,13 @@ static void build_dsdt(GArray *table_data,
socket_count = riscv_socket_count(ms);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
- acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base,
- memmap[VIRT_PLIC].size, "RSCV0001");
+ acpi_dsdt_add_plic_aplic(scope, socket_count, s->num_sources,
+ memmap[VIRT_PLIC].base,
+ memmap[VIRT_PLIC].size,
+ "RSCV0001");
} else {
- acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base,
+ acpi_dsdt_add_plic_aplic(scope, socket_count, s->num_sources,
+ memmap[VIRT_APLIC_S].base,
memmap[VIRT_APLIC_S].size, "RSCV0002");
}
@@ -494,15 +501,15 @@ static void build_dsdt(GArray *table_data,
} else if (socket_count == 2) {
virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
memmap[VIRT_VIRTIO].size,
- VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_IRQ + s->num_sources, 0,
VIRTIO_COUNT);
- acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources);
} else {
virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base,
memmap[VIRT_VIRTIO].size,
- VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0,
+ VIRTIO_IRQ + s->num_sources, 0,
VIRTIO_COUNT);
- acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2);
+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2);
}
aml_append(dsdt, scope);
@@ -581,7 +588,7 @@ static void build_madt(GArray *table_data,
for (socket = 0; socket < riscv_socket_count(ms); socket++) {
aplic_addr = s->memmap[VIRT_APLIC_S].base +
s->memmap[VIRT_APLIC_S].size * socket;
- gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ gsi_base = s->num_sources * socket;
build_append_int_noprefix(table_data, 0x1A, 1); /* Type */
build_append_int_noprefix(table_data, 36, 1); /* Length */
build_append_int_noprefix(table_data, 1, 1); /* Version */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ce0fd6f50c..6c5bcd43dc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1548,6 +1548,7 @@ static void virt_machine_init(MachineState *machine)
} else {
s->irqchip[i] = riscv_create_aia(s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC,
s->aia_guests,
+ s->num_sources,
&s->memmap[VIRT_APLIC_M],
&s->memmap[VIRT_APLIC_S],
&s->memmap[VIRT_IMSIC_M],
@@ -1691,6 +1692,7 @@ static void virt_machine_instance_init(Object *obj)
s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
s->acpi = ON_OFF_AUTO_AUTO;
s->iommu_sys = ON_OFF_AUTO_AUTO;
+ s->num_sources = VIRT_IRQCHIP_NUM_SOURCES;
}
static char *virt_get_aia_guests(Object *obj, Error **errp)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index ad858deb76..36a2def410 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -64,6 +64,7 @@ struct RISCVVirtState {
struct GPEXHost *gpex_host;
OnOffAuto iommu_sys;
uint16_t pci_iommu_bdf;
+ uint16_t num_sources;
};
enum {
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 5/9] target/riscv: tt-ascalon: Enable Zkr extension
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (3 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 4/9] hw/riscv/aia: Provide number of irq sources Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade Nicholas Piggin
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley
Ascalon supports Zkr and the SEED CSR.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ce15a17c37..69649462dd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3190,6 +3190,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_zba = true,
.cfg.ext_zbb = true,
.cfg.ext_zbs = true,
+ .cfg.ext_zkr = true,
.cfg.ext_zkt = true,
.cfg.ext_zvbb = true,
.cfg.ext_zvbc = true,
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (4 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 5/9] target/riscv: tt-ascalon: Enable Zkr extension Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 18:57 ` Andrew Jones
2026-05-07 4:38 ` [PATCH v5 7/9] hw/riscv: Add Tenstorrent Atlantis machine Nicholas Piggin
` (2 subsequent siblings)
8 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley
Ascalon supports Svadu (hardware A/D bit updates).
QEMU makes Svadu and Svade mutually exclusive, remove Svade so
Ascalon comes up with Svadu working.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69649462dd..97e3567264 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3204,7 +3204,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_ssaia = true,
.cfg.ext_sscofpmf = true,
.cfg.ext_sstc = true,
- .cfg.ext_svade = true,
.cfg.ext_svinval = true,
.cfg.ext_svnapot = true,
.cfg.ext_svpbmt = true,
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade
2026-05-07 4:38 ` [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade Nicholas Piggin
@ 2026-05-07 18:57 ` Andrew Jones
2026-05-08 3:54 ` Nicholas Piggin
0 siblings, 1 reply; 14+ messages in thread
From: Andrew Jones @ 2026-05-07 18:57 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Alistair Francis, Daniel Henrique Barboza, Chao Liu,
Michael Ellerman, Joel Stanley, Anirudh Srinivasan,
Portia Stephens, qemu-riscv, qemu-devel, Joel Stanley
On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote:
> Ascalon supports Svadu (hardware A/D bit updates).
>
> QEMU makes Svadu and Svade mutually exclusive, remove Svade so
> Ascalon comes up with Svadu working.
Hi Nicholas,
Svadu and Svade aren't mutually exclusive, you can see the expected
behaviors for the pair in the commit message of commit 70d22fd92c3b
("target/riscv: Gate hardware A/D PTE bit updating"). Does the
Ascalon support Svade? If so, then it's probably best to enable both
and leave it to Linux to enable Svadu with SBI FWFT
SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of
software supported. But, unfortunately Linux doesn't yet support the
checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still
need kernel patches for that.
Thanks,
drew
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 69649462dd..97e3567264 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3204,7 +3204,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.ext_ssaia = true,
> .cfg.ext_sscofpmf = true,
> .cfg.ext_sstc = true,
> - .cfg.ext_svade = true,
> .cfg.ext_svinval = true,
> .cfg.ext_svnapot = true,
> .cfg.ext_svpbmt = true,
> --
> 2.53.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade
2026-05-07 18:57 ` Andrew Jones
@ 2026-05-08 3:54 ` Nicholas Piggin
2026-05-08 13:56 ` Andrew Jones
0 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-08 3:54 UTC (permalink / raw)
To: Andrew Jones
Cc: Alistair Francis, Daniel Henrique Barboza, Chao Liu,
Michael Ellerman, Joel Stanley, Anirudh Srinivasan,
Portia Stephens, qemu-riscv, qemu-devel, Joel Stanley
On Thu, May 07, 2026 at 01:57:02PM -0500, Andrew Jones wrote:
> On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote:
> > Ascalon supports Svadu (hardware A/D bit updates).
> >
> > QEMU makes Svadu and Svade mutually exclusive, remove Svade so
> > Ascalon comes up with Svadu working.
>
> Hi Nicholas,
>
> Svadu and Svade aren't mutually exclusive, you can see the expected
> behaviors for the pair in the commit message of commit 70d22fd92c3b
> ("target/riscv: Gate hardware A/D PTE bit updating").
Okay misunderstood what QEMU is doing. What does it mean for an
implementation to support Svadu && !Svade? AFAIKS the spec says ADUE=0
means the access is performed as though Svade is implemented. I'm either
wrong about that or miss the point why Svadu && Svade is handled
differently in the patch you reference (or both).
> Does the
> Ascalon support Svade? If so, then it's probably best to enable both
> and leave it to Linux to enable Svadu with SBI FWFT
> SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of
> software supported. But, unfortunately Linux doesn't yet support the
> checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still
> need kernel patches for that.
Our docs say it supports both. If enabling both bits is the correct
thing to do we should go with that for upstream.
Thanks,
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade
2026-05-08 3:54 ` Nicholas Piggin
@ 2026-05-08 13:56 ` Andrew Jones
0 siblings, 0 replies; 14+ messages in thread
From: Andrew Jones @ 2026-05-08 13:56 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Alistair Francis, Daniel Henrique Barboza, Chao Liu,
Michael Ellerman, Joel Stanley, Anirudh Srinivasan,
Portia Stephens, qemu-riscv, qemu-devel, Joel Stanley
On Fri, May 08, 2026 at 01:54:30PM +1000, Nicholas Piggin wrote:
> On Thu, May 07, 2026 at 01:57:02PM -0500, Andrew Jones wrote:
> > On Thu, May 07, 2026 at 02:38:34PM +1000, Nicholas Piggin wrote:
> > > Ascalon supports Svadu (hardware A/D bit updates).
> > >
> > > QEMU makes Svadu and Svade mutually exclusive, remove Svade so
> > > Ascalon comes up with Svadu working.
> >
> > Hi Nicholas,
> >
> > Svadu and Svade aren't mutually exclusive, you can see the expected
> > behaviors for the pair in the commit message of commit 70d22fd92c3b
> > ("target/riscv: Gate hardware A/D PTE bit updating").
>
> Okay misunderstood what QEMU is doing. What does it mean for an
> implementation to support Svadu && !Svade? AFAIKS the spec says ADUE=0
> means the access is performed as though Svade is implemented. I'm either
> wrong about that or miss the point why Svadu && Svade is handled
> differently in the patch you reference (or both).
Your question inspired me to go look at the Svadu chapter again and I
see "If the Svadu extension is implemented, the menvcfg.ADUE field is
writable. If the hypervisor extension is additionally implemented, the
henvcfg.ADUE field is also writable". I think at the time I wrote the
patch I either assumed ADUE could be hardwired 1 (which it clearly cannot)
or I decided to preserve the out-of-spec default behavior that QEMU had
been implementing in order to avoid potential for breaking anything
depending on it.
So the four cases in the commit message of 70d22fd92c3b can be summarized
as follows:
(1) Not spec compliant, because commits 0af3f115e68e and 62108f05e74c
effectively hardwired ADUE to 1, but this is the default QEMU
behavior for a long time. Actually, thinking about it more, I doubt
there is much (any) risk in not supporting this case and instead
defaulting to (2) below.
(2) !svade && svadu - this is fine because ADUE is not hardwired to 1.
This just configures svadu at reset. I think this is allowed by the
spec since the *envcfg registers are unspecified on reset, but this
is not what we expect platforms to do.
(3) svade && !svadu - clearly fine, just the svade-only config
(4) svade && svadu - fine, and what we expect platforms to choose for
their reset.
>
> > Does the
> > Ascalon support Svade? If so, then it's probably best to enable both
> > and leave it to Linux to enable Svadu with SBI FWFT
> > SBI_FWFT_PTE_AD_HW_UPDATING in order to maximize the amount of
> > software supported. But, unfortunately Linux doesn't yet support the
> > checking for and enabling of SBI_FWFT_PTE_AD_HW_UPDATING. We still
> > need kernel patches for that.
>
> Our docs say it supports both. If enabling both bits is the correct
> thing to do we should go with that for upstream.
I'll be happy to review the kernel and qemu patches needed to get all
this wired up properly.
Thanks,
drew
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 7/9] hw/riscv: Add Tenstorrent Atlantis machine
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (5 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 6/9] target/riscv: tt-ascalon: Enable Svadu by removing Svade Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload Nicholas Piggin
2026-05-07 4:38 ` [PATCH v5 9/9] tests/functional/riscv64: Add tt-atlantis tests Nicholas Piggin
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley, Philippe Mathieu-Daudé
From: Joel Stanley <joel@jms.id.au>
The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
and CoreLab Technology. It is based on the Atlantis SoC, which includes
the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
RISC-V CPU.
Add the tt-atlantis machine containing serial console, interrupt
controllers, and device tree support.
The Atlantis boot images loaded from include OpenSBI and an initial DTB
that is passed to OpenSBI. This is approximated in the model by having
QEMU build the device tree rather than load a DTB image directly.
Subsequent stages may use the modified DTB provided by OpenSBI or opt to
supply their own.
qemu-system-riscv64 -M tt-atlantis -m 512M \
-kernel Image -initrd rootfs.cpio -nographic
Co-Developed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
---
MAINTAINERS | 10 +
docs/system/riscv/tt_atlantis.rst | 32 ++
docs/system/target-riscv.rst | 1 +
hw/riscv/Kconfig | 10 +
hw/riscv/meson.build | 1 +
hw/riscv/tt_atlantis.c | 556 ++++++++++++++++++++++++++++++
include/hw/riscv/tt_atlantis.h | 51 +++
7 files changed, 661 insertions(+)
create mode 100644 docs/system/riscv/tt_atlantis.rst
create mode 100644 hw/riscv/tt_atlantis.c
create mode 100644 include/hw/riscv/tt_atlantis.h
diff --git a/MAINTAINERS b/MAINTAINERS
index afa178c5cc..1ab5f3e45b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1767,6 +1767,16 @@ F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
F: tests/functional/test_riscv64_sifive_u.py
+Tenstorrent Machines
+M: Joel Stanley <joel@jms.id.au>
+R: Nicholas Piggin <npiggin@gmail.com>
+R: Michael Ellerman <mpe@kernel.org>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: docs/system/riscv/tt_*.rst
+F: hw/riscv/tt_*.c
+F: include/hw/riscv/tt_*.h
+
AMD Microblaze-V Generic Board
M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
S: Maintained
diff --git a/docs/system/riscv/tt_atlantis.rst b/docs/system/riscv/tt_atlantis.rst
new file mode 100644
index 0000000000..e8bc625677
--- /dev/null
+++ b/docs/system/riscv/tt_atlantis.rst
@@ -0,0 +1,32 @@
+Tenstorrent Atlantis (``tt-atlantis``)
+======================================
+
+The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
+and CoreLab Technology. It is based on the Atlantis SoC, which includes
+the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
+
+The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
+RISC-V CPU.
+
+tt-atlantis QEMU model features
+-------------------------------
+
+* 8-core Ascalon-X CPU Cluster
+* RISC-V compliant Advanced Interrupt Architecture
+* 16550A compatible UART
+
+
+Note: the QEMU tt-atlantis machine does not model the platform
+exactly or all devices, but it is undergoing improvement.
+
+Supported software
+------------------
+
+The Tenstorrent Ascalon CPUs avoid proprietary or non-standard
+extensions, so compatibility with existing software is generally
+good. The QEMU tt-atlantis machine works with upstream OpenSBI
+and Linux with default configurations.
+
+The development board hardware will require some implementation
+specific setup in firmware which is being developed and may
+become a requirement or option for the tt-atlantis machine.
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index 3ad5d1ddaf..a8e6b33421 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -71,6 +71,7 @@ undocumented; you can get a complete list by running
riscv/mips
riscv/shakti-c
riscv/sifive_u
+ riscv/tt_atlantis
riscv/virt
riscv/xiangshan-kunminghu
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2518b04175..aaf029c9ed 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -120,6 +120,16 @@ config SPIKE
select RISCV_ACLINT
select SIFIVE_PLIC
+config TENSTORRENT
+ bool
+ default y
+ depends on RISCV64
+ select RISCV_ACLINT
+ select RISCV_APLIC
+ select RISCV_IMSIC
+ select SERIAL_MM
+ select DEVICE_TREE
+
config XIANGSHAN_KUNMINGHU
bool
default y
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index e53c180d0d..026e79591f 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -9,6 +9,7 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
+riscv_ss.add(when: 'CONFIG_TENSTORRENT', if_true: files('tt_atlantis.c'))
riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
new file mode 100644
index 0000000000..43f47fbd75
--- /dev/null
+++ b/hw/riscv/tt_atlantis.c
@@ -0,0 +1,556 @@
+/*
+ * Tenstorrent Atlantis RISC-V System on Chip
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Copyright 2025 Tenstorrent, Joel Stanley <joel@jms.id.au>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/cutils.h"
+#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
+#include "qemu/units.h"
+
+#include "hw/core/boards.h"
+#include "hw/core/loader.h"
+#include "hw/core/sysbus.h"
+
+#include "target/riscv/cpu.h"
+#include "target/riscv/pmu.h"
+
+#include "hw/riscv/boot.h"
+#include "hw/riscv/riscv_hart.h"
+
+#include "hw/char/serial-mm.h"
+#include "hw/intc/riscv_aclint.h"
+#include "hw/intc/riscv_aplic.h"
+
+#include "system/system.h"
+#include "system/device_tree.h"
+
+#include "hw/riscv/tt_atlantis.h"
+
+#include "aia.h"
+
+#define TT_IRQCHIP_NUM_MSIS 255
+#define TT_IRQCHIP_NUM_SOURCES 128
+#define TT_IRQCHIP_NUM_PRIO_BITS 3
+#define TT_IRQCHIP_GUESTS 7 /* aia_guests */
+
+#define FDT_PCI_ADDR_CELLS 3
+#define FDT_PCI_INT_CELLS 1
+#define FDT_MAX_INT_CELLS 2
+#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \
+ 1 + FDT_MAX_INT_CELLS)
+
+#define TT_ACLINT_MTIME_SIZE 0x8050
+#define TT_ACLINT_MTIME 0x0
+#define TT_ACLINT_MTIMECMP 0x8000
+#define TT_ACLINT_TIMEBASE_FREQ 1000000000
+
+static const MemMapEntry tt_atlantis_memmap[] = {
+ /* Keep sorted with :'<,'>!sort -g -k 4 */
+ [TT_ATL_DDR_LO] = { 0x00000000, 0x80000000 },
+ [TT_ATL_BOOTROM] = { 0x80000000, 0x2000 },
+ [TT_ATL_MIMSIC] = { 0xa0000000, 0x200000 },
+ [TT_ATL_ACLINT] = { 0xa2180000, 0x10000 },
+ [TT_ATL_SIMSIC] = { 0xa4000000, 0x200000 },
+ [TT_ATL_TIMER] = { 0xa8020000, 0x10000 },
+ [TT_ATL_UART0] = { 0xb0100000, 0x10000 },
+ [TT_ATL_MAPLIC] = { 0xcc000000, 0x4000000 },
+ [TT_ATL_SAPLIC] = { 0xe8000000, 0x4000000 },
+ [TT_ATL_DDR_HI] = { 0x100000000, 0x1000000000 },
+};
+
+static uint32_t next_phandle(void)
+{
+ static uint32_t phandle = 1;
+ return phandle++;
+}
+
+static void create_fdt_cpus(TTAtlantisState *s, uint32_t *intc_phandles)
+{
+ uint32_t cpu_phandle;
+ void *fdt = MACHINE(s)->fdt;
+
+ for (int cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
+ RISCVCPU *cpu_ptr = &s->soc.harts[cpu];
+ g_autofree char *cpu_name = NULL;
+ g_autofree char *intc_name = NULL;
+
+ cpu_phandle = next_phandle();
+
+ cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc.hartid_base + cpu);
+ qemu_fdt_add_subnode(fdt, cpu_name);
+
+ qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv57");
+
+ riscv_isa_write_fdt(cpu_ptr, fdt, cpu_name);
+
+ qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbom-block-size",
+ cpu_ptr->cfg.cbom_blocksize);
+
+ qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cboz-block-size",
+ cpu_ptr->cfg.cboz_blocksize);
+
+ qemu_fdt_setprop_cell(fdt, cpu_name, "riscv,cbop-block-size",
+ cpu_ptr->cfg.cbop_blocksize);
+
+ qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
+ qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
+ qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc.hartid_base + cpu);
+ qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
+ qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
+
+ intc_phandles[cpu] = next_phandle();
+
+ intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+ qemu_fdt_add_subnode(fdt, intc_name);
+ qemu_fdt_setprop_cell(fdt, intc_name, "phandle",
+ intc_phandles[cpu]);
+ qemu_fdt_setprop_string(fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
+ }
+}
+
+static void create_fdt_memory_node(TTAtlantisState *s,
+ hwaddr addr, hwaddr size)
+{
+ void *fdt = MACHINE(s)->fdt;
+ g_autofree char *name = g_strdup_printf("/memory@%"HWADDR_PRIX, addr);
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, addr, 2, size);
+ qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
+}
+
+static void create_fdt_memory(TTAtlantisState *s)
+{
+ hwaddr size_lo = MACHINE(s)->ram_size;
+ hwaddr size_hi = 0;
+
+ if (size_lo > s->memmap[TT_ATL_DDR_LO].size) {
+ size_lo = s->memmap[TT_ATL_DDR_LO].size;
+ size_hi = MACHINE(s)->ram_size - size_lo;
+ }
+
+ create_fdt_memory_node(s, s->memmap[TT_ATL_DDR_LO].base, size_lo);
+ if (size_hi) {
+ /*
+ * The first part of the HI address is aliased at the LO address
+ * so do not include that as usable memory. Is there any way
+ * (or good reason) to describe that aliasing 2GB with DT?
+ */
+ create_fdt_memory_node(s, s->memmap[TT_ATL_DDR_HI].base + size_lo,
+ size_hi);
+ }
+}
+
+static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles)
+{
+ void *fdt = MACHINE(s)->fdt;
+ g_autofree char *name = NULL;
+ g_autofree uint32_t *aclint_mtimer_cells = NULL;
+ uint32_t aclint_cells_size;
+ hwaddr addr;
+
+ aclint_mtimer_cells = g_new0(uint32_t, s->soc.num_harts * 2);
+
+ for (int cpu = 0; cpu < s->soc.num_harts; cpu++) {
+ aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
+ }
+ aclint_cells_size = s->soc.num_harts * sizeof(uint32_t) * 2;
+
+ addr = s->memmap[TT_ATL_ACLINT].base;
+
+ name = g_strdup_printf("/soc/mtimer@%"HWADDR_PRIX, addr);
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,aclint-mtimer");
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+ 2, addr + TT_ACLINT_MTIME,
+ 2, 0x1000,
+ 2, addr + TT_ACLINT_MTIMECMP,
+ 2, 0x1000);
+ qemu_fdt_setprop(fdt, name, "interrupts-extended",
+ aclint_mtimer_cells, aclint_cells_size);
+}
+
+static void create_fdt_one_imsic(void *fdt, const MemMapEntry *mem, int cpus,
+ uint32_t *intc_phandles, uint32_t msi_phandle,
+ int irq_line, uint32_t imsic_guest_bits)
+{
+ g_autofree char *name = NULL;
+ g_autofree uint32_t *imsic_cells = g_new0(uint32_t, cpus * 2);
+
+ for (int cpu = 0; cpu < cpus; cpu++) {
+ imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ imsic_cells[cpu * 2 + 1] = cpu_to_be32(irq_line);
+ }
+
+ name = g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRIX, mem->base);
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,imsics");
+
+ qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 0);
+ qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop(fdt, name, "msi-controller", NULL, 0);
+ qemu_fdt_setprop(fdt, name, "interrupts-extended",
+ imsic_cells, sizeof(uint32_t) * cpus * 2);
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size);
+ qemu_fdt_setprop_cell(fdt, name, "riscv,num-ids", TT_IRQCHIP_NUM_MSIS);
+
+ if (imsic_guest_bits) {
+ qemu_fdt_setprop_cell(fdt, name, "riscv,guest-index-bits",
+ imsic_guest_bits);
+ }
+ qemu_fdt_setprop_cell(fdt, name, "phandle", msi_phandle);
+}
+
+static void create_fdt_one_aplic(void *fdt,
+ const MemMapEntry *mem,
+ uint32_t msi_phandle,
+ uint32_t *intc_phandles,
+ uint32_t aplic_phandle,
+ uint32_t aplic_child_phandle,
+ int irq_line, int num_harts)
+{
+ g_autofree char *name =
+ g_strdup_printf("/soc/interrupt-controller@%"HWADDR_PRIX, mem->base);
+ g_autofree uint32_t *aplic_cells = g_new0(uint32_t, num_harts * 2);
+
+ for (int cpu = 0; cpu < num_harts; cpu++) {
+ aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ aplic_cells[cpu * 2 + 1] = cpu_to_be32(irq_line);
+ }
+
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "riscv,aplic");
+ qemu_fdt_setprop_cell(fdt, name, "#address-cells", 0);
+ qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", 2);
+ qemu_fdt_setprop(fdt, name, "interrupt-controller", NULL, 0);
+
+ qemu_fdt_setprop(fdt, name, "interrupts-extended",
+ aplic_cells, num_harts * sizeof(uint32_t) * 2);
+ qemu_fdt_setprop_cell(fdt, name, "msi-parent", msi_phandle);
+
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size);
+ qemu_fdt_setprop_cell(fdt, name, "riscv,num-sources",
+ TT_IRQCHIP_NUM_SOURCES);
+
+ if (aplic_child_phandle) {
+ qemu_fdt_setprop_cell(fdt, name, "riscv,children",
+ aplic_child_phandle);
+ qemu_fdt_setprop_cells(fdt, name, "riscv,delegation",
+ aplic_child_phandle, 1, TT_IRQCHIP_NUM_SOURCES);
+ }
+
+ qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle);
+}
+
+static void create_fdt_pmu(TTAtlantisState *s)
+{
+ g_autofree char *pmu_name = g_strdup_printf("/pmu");
+ void *fdt = MACHINE(s)->fdt;
+ RISCVCPU *hart = &s->soc.harts[0];
+
+ qemu_fdt_add_subnode(fdt, pmu_name);
+ qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu");
+ riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name);
+}
+
+static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap,
+ uint32_t aplic_s_phandle,
+ uint32_t imsic_s_phandle)
+{
+ MachineState *ms = MACHINE(s);
+ void *fdt = MACHINE(s)->fdt;
+ g_autofree uint32_t *intc_phandles = NULL;
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
+ TT_ACLINT_TIMEBASE_FREQ);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ intc_phandles = g_new0(uint32_t, ms->smp.cpus);
+
+ create_fdt_cpus(s, intc_phandles);
+
+ create_fdt_memory(s);
+
+ create_fdt_aclint(s, intc_phandles);
+
+ /* M-level IMSIC node */
+ uint32_t msi_m_phandle = next_phandle();
+ create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus,
+ intc_phandles, msi_m_phandle,
+ IRQ_M_EXT, 0);
+
+ /* S-level IMSIC node */
+ create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus,
+ intc_phandles, imsic_s_phandle,
+ IRQ_S_EXT, imsic_num_bits(TT_IRQCHIP_GUESTS + 1));
+
+ uint32_t aplic_m_phandle = next_phandle();
+
+ /* M-level APLIC node */
+ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC],
+ msi_m_phandle, intc_phandles,
+ aplic_m_phandle, aplic_s_phandle,
+ IRQ_M_EXT, s->soc.num_harts);
+
+ /* S-level APLIC node */
+ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC],
+ imsic_s_phandle, intc_phandles,
+ aplic_s_phandle, 0,
+ IRQ_S_EXT, s->soc.num_harts);
+}
+
+static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq,
+ int irqchip_phandle)
+{
+ g_autofree char *name = g_strdup_printf("/soc/serial@%"HWADDR_PRIX,
+ mem->base);
+
+ qemu_fdt_add_subnode(fdt, name);
+ qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg", 2, mem->base, 2, mem->size);
+ qemu_fdt_setprop_cell(fdt, name, "reg-shift", 2);
+ qemu_fdt_setprop_cell(fdt, name, "reg-io-width", 4);
+ qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
+ qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", irqchip_phandle);
+ qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x4);
+
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
+ qemu_fdt_setprop_string(fdt, "/aliases", "serial0", name);
+}
+
+static void finalize_fdt(TTAtlantisState *s)
+{
+ uint32_t aplic_s_phandle = next_phandle();
+ uint32_t imsic_s_phandle = next_phandle();
+ void *fdt = MACHINE(s)->fdt;
+
+ create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle);
+
+ /*
+ * We want to do this, but the Linux aplic driver was broken before v6.16
+ *
+ * qemu_fdt_setprop_cell(MACHINE(s)->fdt, "/soc", "interrupt-parent",
+ * aplic_s_phandle);
+ */
+
+ create_fdt_uart(fdt, &s->memmap[TT_ATL_UART0], TT_ATL_UART0_IRQ,
+ aplic_s_phandle);
+}
+
+static void create_fdt(TTAtlantisState *s)
+{
+ MachineState *ms = MACHINE(s);
+ uint8_t rng_seed[32];
+ g_autofree char *name = NULL;
+ void *fdt;
+
+ fdt = create_device_tree(&s->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+ ms->fdt = fdt;
+
+ qemu_fdt_setprop_string(fdt, "/", "model",
+ "Tenstorrent Atlantis RISC-V Machine");
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "tenstorrent,atlantis");
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
+
+ qemu_fdt_add_subnode(fdt, "/soc");
+ qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
+ qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+
+ /* Pass seed to RNG */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+
+ qemu_fdt_add_subnode(fdt, "/aliases");
+
+ create_fdt_pmu(s);
+}
+
+static void tt_atlantis_machine_done(Notifier *notifier, void *data)
+{
+ TTAtlantisState *s = container_of(notifier, TTAtlantisState, machine_done);
+ MachineState *machine = MACHINE(s);
+ hwaddr start_addr = s->memmap[TT_ATL_DDR_LO].base;
+ hwaddr mem_size;
+ target_ulong firmware_end_addr, kernel_start_addr;
+ const char *firmware_name = riscv_default_firmware_name(&s->soc);
+ uint64_t fdt_load_addr;
+ uint64_t kernel_entry;
+ RISCVBootInfo boot_info;
+
+ /*
+ * A user provided dtb must include everything, including
+ * dynamic sysbus devices. Our FDT needs to be finalized.
+ */
+ if (machine->dtb == NULL) {
+ finalize_fdt(s);
+ }
+
+ mem_size = machine->ram_size;
+ if (mem_size > s->memmap[TT_ATL_DDR_LO].size) {
+ mem_size = s->memmap[TT_ATL_DDR_LO].size;
+ }
+ riscv_boot_info_init_discontig_mem(&boot_info, &s->soc,
+ s->memmap[TT_ATL_DDR_LO].base,
+ mem_size);
+
+ firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info,
+ firmware_name,
+ &start_addr, NULL);
+
+ kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
+ firmware_end_addr);
+ if (machine->kernel_filename) {
+ riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+ true, NULL);
+ }
+ kernel_entry = boot_info.image_low_addr;
+
+ fdt_load_addr = riscv_compute_fdt_addr(s->memmap[TT_ATL_DDR_LO].base,
+ s->memmap[TT_ATL_DDR_LO].size,
+ machine, &boot_info);
+ riscv_load_fdt(fdt_load_addr, machine->fdt);
+
+ /* load the reset vector */
+ riscv_setup_rom_reset_vec(machine, &s->soc, start_addr,
+ s->memmap[TT_ATL_BOOTROM].base,
+ s->memmap[TT_ATL_BOOTROM].size,
+ kernel_entry,
+ fdt_load_addr);
+
+}
+
+static void tt_atlantis_machine_init(MachineState *machine)
+{
+ TTAtlantisState *s = TT_ATLANTIS_MACHINE(machine);
+
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
+ MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
+ MemoryRegion *bootrom = g_new(MemoryRegion, 1);
+ ram_addr_t lo_ram_size, hi_ram_size;
+ int hart_count = machine->smp.cpus;
+ int base_hartid = 0;
+
+ s->memmap = tt_atlantis_memmap;
+
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
+ TYPE_RISCV_HART_ARRAY);
+ object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
+ &error_abort);
+ object_property_set_int(OBJECT(&s->soc), "hartid-base", base_hartid,
+ &error_abort);
+ object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count,
+ &error_abort);
+ object_property_set_int(OBJECT(&s->soc), "resetvec",
+ s->memmap[TT_ATL_BOOTROM].base,
+ &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
+
+ s->irqchip = riscv_create_aia(true, TT_IRQCHIP_GUESTS,
+ TT_IRQCHIP_NUM_SOURCES,
+ &s->memmap[TT_ATL_MAPLIC],
+ &s->memmap[TT_ATL_SAPLIC],
+ &s->memmap[TT_ATL_MIMSIC],
+ &s->memmap[TT_ATL_SIMSIC],
+ 0, base_hartid, hart_count,
+ TT_IRQCHIP_NUM_MSIS,
+ TT_IRQCHIP_NUM_PRIO_BITS);
+
+ riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base,
+ TT_ACLINT_MTIME_SIZE,
+ base_hartid, hart_count,
+ TT_ACLINT_MTIMECMP,
+ TT_ACLINT_MTIME,
+ TT_ACLINT_TIMEBASE_FREQ, true);
+
+ /* DDR */
+
+ /* The high address covers all of RAM, the low address just the first 2GB */
+ lo_ram_size = s->memmap[TT_ATL_DDR_LO].size;
+ hi_ram_size = s->memmap[TT_ATL_DDR_HI].size;
+ if (machine->ram_size > hi_ram_size) {
+ char *sz = size_to_str(hi_ram_size);
+ error_report("RAM size is too large, maximum is %s", sz);
+ g_free(sz);
+ exit(EXIT_FAILURE);
+ }
+
+ memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->ram,
+ 0, lo_ram_size);
+ memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine->ram,
+ 0, hi_ram_size);
+ memory_region_add_subregion(system_memory,
+ s->memmap[TT_ATL_DDR_LO].base, ram_lo);
+ memory_region_add_subregion(system_memory,
+ s->memmap[TT_ATL_DDR_HI].base, ram_hi);
+
+ /* Boot ROM */
+ memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom",
+ s->memmap[TT_ATL_BOOTROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, s->memmap[TT_ATL_BOOTROM].base,
+ bootrom);
+
+ /* UART */
+ serial_mm_init(system_memory, s->memmap[TT_ATL_UART0].base, 2,
+ qdev_get_gpio_in(s->irqchip, TT_ATL_UART0_IRQ),
+ 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+ /* Load or create device tree */
+ if (machine->dtb) {
+ machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
+ if (!machine->fdt) {
+ error_report("load_device_tree() failed");
+ exit(1);
+ }
+ } else {
+ create_fdt(s);
+ }
+
+ s->machine_done.notify = tt_atlantis_machine_done;
+ qemu_add_machine_init_done_notifier(&s->machine_done);
+}
+
+static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "Tenstorrent Atlantis RISC-V SoC";
+ mc->init = tt_atlantis_machine_init;
+ mc->max_cpus = 8;
+ mc->default_cpus = 8;
+ mc->default_ram_size = 2 * GiB;
+ mc->default_cpu_type = TYPE_RISCV_CPU_TT_ASCALON;
+ mc->block_default_type = IF_VIRTIO;
+ mc->no_cdrom = 1;
+ mc->default_ram_id = "tt_atlantis.ram";
+}
+
+static const TypeInfo tt_atlantis_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("tt-atlantis"),
+ .parent = TYPE_MACHINE,
+ .class_init = tt_atlantis_machine_class_init,
+ .instance_size = sizeof(TTAtlantisState),
+ },
+};
+
+DEFINE_TYPES(tt_atlantis_types)
diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h
new file mode 100644
index 0000000000..960dc07841
--- /dev/null
+++ b/include/hw/riscv/tt_atlantis.h
@@ -0,0 +1,51 @@
+/*
+ * Tenstorrent Atlantis RISC-V System on Chip
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Copyright 2025 Tenstorrent, Joel Stanley <joel@jms.id.au>
+ */
+
+#ifndef HW_RISCV_TT_ATLANTIS_H
+#define HW_RISCV_TT_ATLANTIS_H
+
+#include "hw/core/boards.h"
+#include "hw/core/sysbus.h"
+#include "hw/intc/riscv_imsic.h"
+#include "hw/riscv/riscv_hart.h"
+
+#define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis")
+OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE)
+
+struct TTAtlantisState {
+ /*< private >*/
+ MachineState parent;
+
+ /*< public >*/
+ Notifier machine_done;
+ const MemMapEntry *memmap;
+
+ RISCVHartArrayState soc;
+ DeviceState *irqchip;
+
+ int fdt_size;
+};
+
+enum {
+ TT_ATL_UART0_IRQ = 38,
+};
+
+enum {
+ TT_ATL_ACLINT,
+ TT_ATL_BOOTROM,
+ TT_ATL_DDR_LO,
+ TT_ATL_DDR_HI,
+ TT_ATL_MAPLIC,
+ TT_ATL_MIMSIC,
+ TT_ATL_SAPLIC,
+ TT_ATL_SIMSIC,
+ TT_ATL_TIMER,
+ TT_ATL_UART0,
+};
+
+#endif
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (6 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 7/9] hw/riscv: Add Tenstorrent Atlantis machine Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
2026-05-07 6:09 ` Philippe Mathieu-Daudé
2026-05-07 4:38 ` [PATCH v5 9/9] tests/functional/riscv64: Add tt-atlantis tests Nicholas Piggin
8 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Joel Stanley
OpenSBI hangs before any console output if the domain init code sees the
next stage is not in an executable region.
If no kernel payload is provided to QEMU, the next stage address is
NULL, and the riscv virt machine memory map ends up covering the 0
address with the catch all S-mode RWX region and so OpenSBI prints
console messages and does not hang until the next stage boot.
The Tenstorrent Atlantis machine address map has RAM starting at 0 and
it loads OpenSBI there, so it is M-mode and not accessible by S-mode,
tripping the early check and hang.
Add a helper to set up a simple payload that gets OpenSBI messages to
console, until OpenSBI can be fixed.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
hw/riscv/tt_atlantis.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 43f47fbd75..789a66870a 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -384,6 +384,30 @@ static void create_fdt(TTAtlantisState *s)
create_fdt_pmu(s);
}
+/*
+ * This works around a problem with OpenSBI hanging with no console output if
+ * no payload is provided. By chance, machines with memory at 0x80000000 do get
+ * output, but Atlantis memory begins at 0x0 which takes a different OpenSBI
+ * error path.
+ *
+ * This can be removed when OpenSBI is fixed in QEMU.
+ */
+static void tt_atlantis_setup_halting_payload_opensbi_fixup(
+ RISCVBootInfo *info, hwaddr addr)
+{
+ /* Store the payload vector in little_endian byte order */
+ static const uint32_t payload_vec[] = {
+ const_le32(0x10500073), /* 1: wfi */
+ const_le32(0xffdff06f), /* j 1b */
+ };
+ rom_add_blob_fixed_as("mrom.payload", payload_vec, sizeof(payload_vec),
+ addr, &address_space_memory);
+
+ info->kernel_size = sizeof(payload_vec);
+ info->image_low_addr = addr;
+ info->image_high_addr = info->image_low_addr + info->kernel_size;
+}
+
static void tt_atlantis_machine_done(Notifier *notifier, void *data)
{
TTAtlantisState *s = container_of(notifier, TTAtlantisState, machine_done);
@@ -421,6 +445,9 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data)
if (machine->kernel_filename) {
riscv_load_kernel(machine, &boot_info, kernel_start_addr,
true, NULL);
+ } else {
+ tt_atlantis_setup_halting_payload_opensbi_fixup(&boot_info,
+ kernel_start_addr);
}
kernel_entry = boot_info.image_low_addr;
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload
2026-05-07 4:38 ` [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload Nicholas Piggin
@ 2026-05-07 6:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 14+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-05-07 6:09 UTC (permalink / raw)
To: Nicholas Piggin, Alistair Francis, Daniel Henrique Barboza
Cc: Chao Liu, Michael Ellerman, Joel Stanley, Anirudh Srinivasan,
Portia Stephens, qemu-riscv, qemu-devel, Joel Stanley
On 7/5/26 06:38, Nicholas Piggin wrote:
> OpenSBI hangs before any console output if the domain init code sees the
> next stage is not in an executable region.
>
> If no kernel payload is provided to QEMU, the next stage address is
> NULL, and the riscv virt machine memory map ends up covering the 0
> address with the catch all S-mode RWX region and so OpenSBI prints
> console messages and does not hang until the next stage boot.
>
> The Tenstorrent Atlantis machine address map has RAM starting at 0 and
> it loads OpenSBI there, so it is M-mode and not accessible by S-mode,
> tripping the early check and hang.
>
> Add a helper to set up a simple payload that gets OpenSBI messages to
> console, until OpenSBI can be fixed.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> hw/riscv/tt_atlantis.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 9/9] tests/functional/riscv64: Add tt-atlantis tests
2026-05-07 4:38 [PATCH v5 0/9] hw/riscv: Add the Tenstorrent Atlantis machine Nicholas Piggin
` (7 preceding siblings ...)
2026-05-07 4:38 ` [PATCH v5 8/9] hw/riscv/atlantis: Provide a simple halting payload Nicholas Piggin
@ 2026-05-07 4:38 ` Nicholas Piggin
8 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2026-05-07 4:38 UTC (permalink / raw)
To: Alistair Francis, Daniel Henrique Barboza
Cc: Nicholas Piggin, Chao Liu, Michael Ellerman, Joel Stanley,
Anirudh Srinivasan, Portia Stephens, qemu-riscv, qemu-devel,
Philippe Mathieu-Daudé, Joel Stanley
Add OpenSBI and Linux boot tests for the tt-atlantis machine.
Based on tests/functional/riscv64/test_sifive_u.py.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
MAINTAINERS | 1 +
tests/functional/riscv64/meson.build | 1 +
tests/functional/riscv64/test_opensbi.py | 4 ++
tests/functional/riscv64/test_tt_atlantis.py | 57 ++++++++++++++++++++
4 files changed, 63 insertions(+)
create mode 100755 tests/functional/riscv64/test_tt_atlantis.py
diff --git a/MAINTAINERS b/MAINTAINERS
index 1ab5f3e45b..e106cadb81 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1776,6 +1776,7 @@ S: Supported
F: docs/system/riscv/tt_*.rst
F: hw/riscv/tt_*.c
F: include/hw/riscv/tt_*.h
+F: tests/functional/riscv64/test_tt_*.py
AMD Microblaze-V Generic Board
M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
diff --git a/tests/functional/riscv64/meson.build b/tests/functional/riscv64/meson.build
index b996c89d7d..c4456fabd7 100644
--- a/tests/functional/riscv64/meson.build
+++ b/tests/functional/riscv64/meson.build
@@ -13,5 +13,6 @@ tests_riscv64_system_quick = [
tests_riscv64_system_thorough = [
'boston',
'sifive_u',
+ 'tt_atlantis',
'tuxrun',
]
diff --git a/tests/functional/riscv64/test_opensbi.py b/tests/functional/riscv64/test_opensbi.py
index d077e40f42..0f8beb7e7a 100755
--- a/tests/functional/riscv64/test_opensbi.py
+++ b/tests/functional/riscv64/test_opensbi.py
@@ -28,6 +28,10 @@ def test_riscv_sifive_u(self):
self.set_machine('sifive_u')
self.boot_opensbi()
+ def test_riscv_tt_atlantis(self):
+ self.set_machine('tt-atlantis')
+ self.boot_opensbi()
+
def test_riscv_virt(self):
self.set_machine('virt')
self.boot_opensbi()
diff --git a/tests/functional/riscv64/test_tt_atlantis.py b/tests/functional/riscv64/test_tt_atlantis.py
new file mode 100755
index 0000000000..48abd5cd27
--- /dev/null
+++ b/tests/functional/riscv64/test_tt_atlantis.py
@@ -0,0 +1,57 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots a Linux kernel on a Tenstorrent Atlantis machine
+# and checks the console
+#
+# Copyright (c) Linaro Ltd.
+# Copyright 2026 Tenstorrent
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset, LinuxKernelTest
+
+
+class TTAtlantis(LinuxKernelTest):
+
+ ASSET_KERNEL = Asset(
+ 'https://storage.tuxboot.com/kernels/6.11.9/riscv64/Image',
+ '174f8bb87f08961e54fa3fcd954a8e31f4645f6d6af4dd43983d5e9841490fb0')
+ ASSET_ROOTFS = Asset(
+ ('https://github.com/groeck/linux-build-test/raw/'
+ '9819da19e6eef291686fdd7b029ea00e764dc62f/rootfs/riscv64/'
+ 'rootfs.ext2.gz'),
+ 'b6ed95610310b7956f9bf20c4c9c0c05fea647900df441da9dfe767d24e8b28b')
+
+ def do_test_riscv64_tt_atlantis(self, connect_disk):
+ self.set_machine('tt-atlantis')
+ kernel_path = self.ASSET_KERNEL.fetch()
+ rootfs_path = self.uncompress(self.ASSET_ROOTFS)
+
+ self.vm.set_console()
+ kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'earlycon=sbi '
+
+ if connect_disk:
+ kernel_command_line += 'root=/dev/vda panic=-1 noreboot rootwait '
+ self.vm.add_args('-device',
+ 'virtio-blk,drive=drive0,serial=0x1234,bus=pcie.0')
+ self.vm.add_args('-drive',
+ f'file={rootfs_path},if=none,id=drive0,format=raw')
+ pattern = 'Boot successful.'
+ else:
+ kernel_command_line += 'panic=0 noreboot '
+ pattern = 'Cannot open root device'
+
+ self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line,
+ '-no-reboot')
+
+ self.vm.launch()
+ self.wait_for_console_pattern(pattern)
+
+ def test_riscv64_tt_atlantis(self):
+ # tt-atlantis machine has no PCI host yet, so no disk
+ self.do_test_riscv64_tt_atlantis(False)
+
+
+if __name__ == '__main__':
+ LinuxKernelTest.main()
--
2.53.0
^ permalink raw reply related [flat|nested] 14+ messages in thread