From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v2 01/12] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
Date: Tue, 12 May 2026 01:35:10 -0700 [thread overview]
Message-ID: <20260512083521.3448-2-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260512083521.3448-1-changhuang.liang@starfivetech.com>
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../soc/starfive/starfive,jhb100-syscon.yaml | 107 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..0add3d9727ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The StarFive JHB100 SoC system controller contains MMIO registers used by
+ other hardware modules (e.g., PLL, eMMC, PCIe). These modules access
+ specific register offsets, bit masks, and shifts within the system
+ controller region for configuration and status.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jhb100-b2h-syscon
+ - starfive,jhb100-gpu-syscon
+ - starfive,jhb100-h2b-syscon
+ - starfive,jhb100-host-syscon
+ - starfive,jhb100-husb-syscon
+ - starfive,jhb100-husbcmn-syscon
+ - starfive,jhb100-husbd-syscon
+ - starfive,jhb100-npu-syscon
+ - starfive,jhb100-pcieep-ecsr-syscon
+ - starfive,jhb100-pcierp-ecsr-syscon
+ - starfive,jhb100-pcierp-syscon
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-per2-syscon
+ - starfive,jhb100-per3-syscon
+ - starfive,jhb100-strap-syscon
+ - starfive,jhb100-sys0-syscon
+ - starfive,jhb100-sys1-syscon
+ - starfive,jhb100-sys2-syscon
+ - starfive,jhb100-usb-syscon
+ - starfive,jhb100-vout-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - clocks
+ - '#clock-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-pcierp-syscon
+ then:
+ required:
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@13010000 {
+ compatible = "starfive,jhb100-sys0-syscon", "syscon";
+ reg = <0x13010000 0x2000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ syscon@13014000 {
+ compatible = "starfive,jhb100-sys1-syscon", "syscon";
+ reg = <0x13014000 0x4000>;
+ };
+
+ syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon";
+ reg = <0x11719000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 47e4b368347f..6f6aac7cea95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25613,6 +25613,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SYSCON
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
Inochi Amaoto <inochiama@gmail.com>,
Alexey Charkov <alchark@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Keguang Zhang <keguang.zhang@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v2 01/12] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
Date: Tue, 12 May 2026 01:35:10 -0700 [thread overview]
Message-ID: <20260512083521.3448-2-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260512083521.3448-1-changhuang.liang@starfivetech.com>
Add documentation to describe StarFive JHB100 SoC System Controller
Registers.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
.../soc/starfive/starfive,jhb100-syscon.yaml | 107 ++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
new file mode 100644
index 000000000000..0add3d9727ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 SoC system controller
+
+maintainers:
+ - Kevin Xie <kevin.xie@starfivetech.com>
+ - Changhuang Liang <changhuang.liang@starfivetech.com>
+
+description:
+ The StarFive JHB100 SoC system controller contains MMIO registers used by
+ other hardware modules (e.g., PLL, eMMC, PCIe). These modules access
+ specific register offsets, bit masks, and shifts within the system
+ controller region for configuration and status.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - starfive,jhb100-b2h-syscon
+ - starfive,jhb100-gpu-syscon
+ - starfive,jhb100-h2b-syscon
+ - starfive,jhb100-host-syscon
+ - starfive,jhb100-husb-syscon
+ - starfive,jhb100-husbcmn-syscon
+ - starfive,jhb100-husbd-syscon
+ - starfive,jhb100-npu-syscon
+ - starfive,jhb100-pcieep-ecsr-syscon
+ - starfive,jhb100-pcierp-ecsr-syscon
+ - starfive,jhb100-pcierp-syscon
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-per2-syscon
+ - starfive,jhb100-per3-syscon
+ - starfive,jhb100-strap-syscon
+ - starfive,jhb100-sys0-syscon
+ - starfive,jhb100-sys1-syscon
+ - starfive,jhb100-sys2-syscon
+ - starfive,jhb100-usb-syscon
+ - starfive,jhb100-vout-syscon
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jhb100-per0-syscon
+ - starfive,jhb100-per1-syscon
+ - starfive,jhb100-sys0-syscon
+ then:
+ required:
+ - clocks
+ - '#clock-cells'
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: starfive,jhb100-pcierp-syscon
+ then:
+ required:
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@13010000 {
+ compatible = "starfive,jhb100-sys0-syscon", "syscon";
+ reg = <0x13010000 0x2000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
+ syscon@13014000 {
+ compatible = "starfive,jhb100-sys1-syscon", "syscon";
+ reg = <0x13014000 0x4000>;
+ };
+
+ syscon@11719000 {
+ compatible = "starfive,jhb100-pcierp-syscon", "syscon";
+ reg = <0x11719000 0x1000>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 47e4b368347f..6f6aac7cea95 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25613,6 +25613,11 @@ S: Maintained
F: drivers/reset/starfive/reset-starfive-jhb1*
F: include/dt-bindings/reset/starfive,jhb1*.h
+STARFIVE JHB100 SYSCON
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-05-12 8:35 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang [this message]
2026-05-12 8:35 ` [PATCH v2 01/12] dt-bindings: soc: starfive: " Changhuang Liang
2026-05-12 17:38 ` Conor Dooley
2026-05-12 17:38 ` Conor Dooley
2026-05-12 8:35 ` [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-14 14:25 ` Krzysztof Kozlowski
2026-05-14 14:25 ` Krzysztof Kozlowski
2026-05-15 3:27 ` Changhuang Liang
2026-05-15 3:27 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 03/12] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-14 14:25 ` Krzysztof Kozlowski
2026-05-14 14:25 ` Krzysztof Kozlowski
2026-05-12 8:35 ` [PATCH v2 05/12] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 06/12] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 07/12] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 08/12] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 09/12] reset: starfive: Introduce assert_polarity Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-15 9:24 ` Philipp Zabel
2026-05-15 9:24 ` Philipp Zabel
2026-05-12 8:35 ` [PATCH v2 10/12] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 8:35 ` [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 17:45 ` Conor Dooley
2026-05-12 17:45 ` Conor Dooley
2026-05-13 1:01 ` Changhuang Liang
2026-05-13 1:01 ` Changhuang Liang
2026-05-13 19:16 ` Conor Dooley
2026-05-13 19:16 ` Conor Dooley
2026-05-14 1:07 ` Changhuang Liang
2026-05-14 1:07 ` Changhuang Liang
2026-05-14 17:50 ` Conor Dooley
2026-05-14 17:50 ` Conor Dooley
2026-05-12 8:35 ` [PATCH v2 12/12] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-05-12 8:35 ` Changhuang Liang
2026-05-12 17:40 ` [PATCH v2 00/12] Add StarFive JHB100 syscon modules Conor Dooley
2026-05-12 17:40 ` Conor Dooley
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