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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Alexey Charkov <alchark@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Keguang Zhang <keguang.zhang@gmail.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock
Date: Thu, 14 May 2026 16:25:21 +0200	[thread overview]
Message-ID: <6f891c51-8149-4c53-ba1f-7c76f50091c4@kernel.org> (raw)
In-Reply-To: <20260512083521.3448-3-changhuang.liang@starfivetech.com>

On 12/05/2026 10:35, Changhuang Liang wrote:
> Add system-0 domain PLL clock for StarFive JHB100 SoC.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
>  include/dt-bindings/clock/starfive,jhb100-crg.h | 6 ++++++
>  1 file changed, 6 insertions(+)


Why isn't this added with the binding for this device?

Best regards,
Krzysztof

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linux-riscv@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney@redhat.com>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Emil Renner Berthing <kernel@esmil.dk>
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Inochi Amaoto <inochiama@gmail.com>,
	Alexey Charkov <alchark@gmail.com>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Keguang Zhang <keguang.zhang@gmail.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock
Date: Thu, 14 May 2026 16:25:21 +0200	[thread overview]
Message-ID: <6f891c51-8149-4c53-ba1f-7c76f50091c4@kernel.org> (raw)
In-Reply-To: <20260512083521.3448-3-changhuang.liang@starfivetech.com>

On 12/05/2026 10:35, Changhuang Liang wrote:
> Add system-0 domain PLL clock for StarFive JHB100 SoC.
> 
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
>  include/dt-bindings/clock/starfive,jhb100-crg.h | 6 ++++++
>  1 file changed, 6 insertions(+)


Why isn't this added with the binding for this device?

Best regards,
Krzysztof

  reply	other threads:[~2026-05-14 14:25 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-12  8:35 [PATCH v2 00/12] Add StarFive JHB100 syscon modules Changhuang Liang
2026-05-12  8:35 ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 01/12] dt-bindings: soc: starfive: " Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12 17:38   ` Conor Dooley
2026-05-12 17:38     ` Conor Dooley
2026-05-12  8:35 ` [PATCH v2 02/12] dt-bindings: clock: Add system-0 domain PLL clock Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-14 14:25   ` Krzysztof Kozlowski [this message]
2026-05-14 14:25     ` Krzysztof Kozlowski
2026-05-15  3:27     ` Changhuang Liang
2026-05-15  3:27       ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 03/12] clk: starfive: Add system-0 domain PLL clock driver Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 04/12] dt-bindings: clock: Add peripheral-0 domain PLL clock Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-14 14:25   ` Krzysztof Kozlowski
2026-05-14 14:25     ` Krzysztof Kozlowski
2026-05-12  8:35 ` [PATCH v2 05/12] clk: starfive: Add peripheral-0 domain PLL clock driver Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 06/12] dt-bindings: clock: Add peripheral-1 domain PLL clock Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 07/12] clk: starfive: Add Peripheral-1 domain PLL clock driver Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 08/12] dt-bindings: reset: Add StarFive JHB100 reset generator Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 09/12] reset: starfive: Introduce assert_polarity Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-15  9:24   ` Philipp Zabel
2026-05-15  9:24     ` Philipp Zabel
2026-05-12  8:35 ` [PATCH v2 10/12] reset: starfive: Add syscon reset driver support Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12  8:35 ` [PATCH v2 11/12] soc: starfive: Add socinfo driver for JHB100 SoC Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12 17:45   ` Conor Dooley
2026-05-12 17:45     ` Conor Dooley
2026-05-13  1:01     ` Changhuang Liang
2026-05-13  1:01       ` Changhuang Liang
2026-05-13 19:16       ` Conor Dooley
2026-05-13 19:16         ` Conor Dooley
2026-05-14  1:07         ` Changhuang Liang
2026-05-14  1:07           ` Changhuang Liang
2026-05-14 17:50           ` Conor Dooley
2026-05-14 17:50             ` Conor Dooley
2026-05-12  8:35 ` [PATCH v2 12/12] riscv: dts: starfive: jhb100: Add syscon nodes Changhuang Liang
2026-05-12  8:35   ` Changhuang Liang
2026-05-12 17:40 ` [PATCH v2 00/12] Add StarFive JHB100 syscon modules Conor Dooley
2026-05-12 17:40   ` Conor Dooley

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