From: Yixun Lan <dlan@kernel.org>
To: Guodong Xu <guodong@riscstar.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
Guodong Xu <docularxu@outlook.com>
Subject: Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores
Date: Fri, 29 May 2026 06:21:59 +0000 [thread overview]
Message-ID: <20260529062159-GKE3748271@kernel.org> (raw)
In-Reply-To: <CAH1PCMa_RJ0NVNyxkqsXPfrF4tz_69ZbWeqkh8xRCu7bLDkr-A@mail.gmail.com>
Hi Guodong,
On 13:18 Thu 28 May , Guodong Xu wrote:
> On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@riscstar.com> wrote:
> >
> > Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> > provides a forward progress guarantee on LR/SC sequences in main
> > memory regions with cacheability and coherence PMAs.
> >
> > The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> > specification.
>
> For the record, I have tested this change on SpacemiT K3 Pico-ITX.
>
> The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
> boots the kernel with:
>
> locktorture.torture_type=spin_lock locktorture.nwriters_stress=16
>
> driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
> with 0 Fail.
>
> ... ...
> [ 735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 741.195211] Writes: Total: 714319420 Max/Min: 45946599/43679876 Fail: 0
>
I appreciate you give more info about the test, just want to make sure,
for the kernel config, the CONFIG_RISCV_TICKET_SPINLOCKS is not enabled?
so it will fall back to use ziccrse implementation..
--
Yixun Lan (dlan)
WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <dlan@kernel.org>
To: Guodong Xu <guodong@riscstar.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
Guodong Xu <docularxu@outlook.com>
Subject: Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores
Date: Fri, 29 May 2026 06:21:59 +0000 [thread overview]
Message-ID: <20260529062159-GKE3748271@kernel.org> (raw)
In-Reply-To: <CAH1PCMa_RJ0NVNyxkqsXPfrF4tz_69ZbWeqkh8xRCu7bLDkr-A@mail.gmail.com>
Hi Guodong,
On 13:18 Thu 28 May , Guodong Xu wrote:
> On Tue, May 26, 2026 at 3:23 PM Guodong Xu <guodong@riscstar.com> wrote:
> >
> > Add the Ziccrse ISA extension to all eight X100 cores. Ziccrse
> > provides a forward progress guarantee on LR/SC sequences in main
> > memory regions with cacheability and coherence PMAs.
> >
> > The SpacemiT X100 core supports it per the SpacemiT K3 hardware
> > specification.
>
> For the record, I have tested this change on SpacemiT K3 Pico-ITX.
>
> The stress test is run by enabling CONFIG_LOCK_TORTURE_TEST=y then
> boots the kernel with:
>
> locktorture.torture_type=spin_lock locktorture.nwriters_stress=16
>
> driving all 8 harts. It survived sustained torture [ran for ~10 minutes]
> with 0 Fail.
>
> ... ...
> [ 735.588947] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 738.015096] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 739.204713] torture_spin_lock_write_delay: delay = 25 jiffies.
> [ 741.195211] Writes: Total: 714319420 Max/Min: 45946599/43679876 Fail: 0
>
I appreciate you give more info about the test, just want to make sure,
for the kernel config, the CONFIG_RISCV_TICKET_SPINLOCKS is not enabled?
so it will fall back to use ziccrse implementation..
--
Yixun Lan (dlan)
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http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-05-29 6:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 19:22 [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores Guodong Xu
2026-05-26 19:22 ` Guodong Xu
2026-05-28 5:18 ` Guodong Xu
2026-05-28 5:18 ` Guodong Xu
2026-05-29 6:21 ` Yixun Lan [this message]
2026-05-29 6:21 ` Yixun Lan
2026-05-29 13:22 ` Guodong Xu
2026-05-29 13:22 ` Guodong Xu
2026-05-30 3:01 ` Yixun Lan
2026-05-30 3:01 ` Yixun Lan
2026-05-30 3:03 ` Yixun Lan
2026-05-30 3:03 ` Yixun Lan
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