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From: Yixun Lan <dlan@kernel.org>
To: Guodong Xu <guodong@riscstar.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
	Guodong Xu <docularxu@outlook.com>
Subject: Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores
Date: Sat, 30 May 2026 03:01:17 +0000	[thread overview]
Message-ID: <20260530030117-GKF3748271@kernel.org> (raw)
In-Reply-To: <CAH1PCMbNv3pGNvjhr02fiibRS3mt929+C3jwreWePN-3O5eLOw@mail.gmail.com>

Hi Guodong,

On 21:22 Fri 29 May     , Guodong Xu wrote:
> Hi, Yixun
.. 
> 
> Correct. Thanks for double-checking.
> 
> In the above test, CONFIG_RISCV_TICKET_SPINLOCKS was not enabled.
> And since X100 has neither Zabha nor Zacas, the runtime selection in
> riscv_spinlock_init() falls through to the Ziccrse branch.
> 
great, that's what I'd like to check , thanks for confirmation
-- 
Yixun Lan (dlan)

WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <dlan@kernel.org>
To: Guodong Xu <guodong@riscstar.com>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	spacemit@lists.linux.dev, linux-kernel@vger.kernel.org,
	Guodong Xu <docularxu@outlook.com>
Subject: Re: [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores
Date: Sat, 30 May 2026 03:01:17 +0000	[thread overview]
Message-ID: <20260530030117-GKF3748271@kernel.org> (raw)
In-Reply-To: <CAH1PCMbNv3pGNvjhr02fiibRS3mt929+C3jwreWePN-3O5eLOw@mail.gmail.com>

Hi Guodong,

On 21:22 Fri 29 May     , Guodong Xu wrote:
> Hi, Yixun
.. 
> 
> Correct. Thanks for double-checking.
> 
> In the above test, CONFIG_RISCV_TICKET_SPINLOCKS was not enabled.
> And since X100 has neither Zabha nor Zacas, the runtime selection in
> riscv_spinlock_init() falls through to the Ziccrse branch.
> 
great, that's what I'd like to check , thanks for confirmation
-- 
Yixun Lan (dlan)

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-05-30  3:01 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-26 19:22 [PATCH] riscv: dts: spacemit: k3: Add Ziccrse extension for X100 cores Guodong Xu
2026-05-26 19:22 ` Guodong Xu
2026-05-28  5:18 ` Guodong Xu
2026-05-28  5:18   ` Guodong Xu
2026-05-29  6:21   ` Yixun Lan
2026-05-29  6:21     ` Yixun Lan
2026-05-29 13:22     ` Guodong Xu
2026-05-29 13:22       ` Guodong Xu
2026-05-30  3:01       ` Yixun Lan [this message]
2026-05-30  3:01         ` Yixun Lan
2026-05-30  3:03 ` Yixun Lan
2026-05-30  3:03   ` Yixun Lan

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