Re: [PATCH v2 22/37] arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The commit introduces a build failure by referencing an undefined Device Tree label `&pcie1_port0`.
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commit 9033bf5c4daddefb447ddf13a1046f9e3fb9d91c
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node

The commit moves PCIe GPIO properties from the Root Complex controller node
to the respective root port nodes in the qcs8550-aim300 device tree. It
also renames the perst-gpios property to reset-gpios to match the bindings
for the root port context.

> diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
> index 5eb4626c61290..579b0a4f34ebc 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
[ ... ]
>  &pcie1 {
> -	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> -	wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> -
>  	pinctrl-0 = <&pcie1_default_state>;
>  	pinctrl-names = "default";
>  };
>  
> +&pcie1_port0 {

[Severity: Low]
Will this cause a build failure during dtc compilation?

The &pcie1_port0 label does not appear to be defined in sm8550.dtsi or any
included file at this point in the git history.

While this is fixed later in the patch series by commit
0b50a2794d4f364375fa966171b8c7483fa1b1b6 ("arm64: dts: qcom: sm8550: Move
PCIe phy and GPIOs to root port node"), does ordering the board patch before
the base SoC dtsi patch break kernel bisectability?

> +	reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-wake-v2-0-2744251b1181@oss.qualcomm.com?part=22