Re: [PATCH v2 33/37] arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The commit message claims that the `phy-names` property is moved to the root port nodes, but the property is actually deleted.
--

commit 0b50a2794d4f364375fa966171b8c7483fa1b1b6
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node

This patch moves the PCIe phy reference and the perst/wake GPIO properties
from the root complex controller node to the root port node. It updates
several sm8550-based device tree files to reflect these moves and renames
perst-gpios to reset-gpios.

>     Move phys and phy-names from the controller to
>     the existing pcieport0 and newly labeled pcie1_port0, allowing

[Severity: Medium]
The commit message states that both phys and phy-names are moved to the root
port nodes. However, phy-names was removed from the controller but never
re-added to the port nodes. Does this omission introduce a regression, or
was the property intentionally dropped?

> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 912525e9bca6f..a8eccaebcf2d7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
[ ... ]
> @@ -2100,6 +2097,8 @@ pcieport0: pcie@0 {
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;
> +
> +				phys = <&pcie0_phy>;

[Severity: Medium]
Should phy-names be included here to match the commit message, or should the
commit message be updated to reflect that phy-names is intentionally dropped?

[ ... ]
> @@ -2288,7 +2284,7 @@ opp-32000000-4 {
>  				};
>  			};
>  
> -			pcie@0 {
> +			pcie1_port0: pcie@0 {
>  				device_type = "pci";
>  				reg = <0x0 0x0 0x0 0x0 0x0>;
>  				bus-range = <0x01 0xff>;
> @@ -2296,6 +2292,8 @@ pcie@0 {
>  				#address-cells = <3>;
>  				#size-cells = <2>;
>  				ranges;
> +
> +				phys = <&pcie1_phy>;

[Severity: Medium]
Similarly for pcie1_port0, should phy-names be added here as well?

>  			};
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260611-wake-v2-0-2744251b1181@oss.qualcomm.com?part=33