From: Stefan Hajnoczi <stefanha@redhat.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Gavin Shan <gshan@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org, jugraham@redhat.com,
shan.gavin@gmail.com, qemu-block@nongnu.org
Subject: Re: [PATCH RFCv1] virtio: Inherit max bounce buffer size from bus parent if possible
Date: Thu, 11 Jun 2026 14:37:08 -0400 [thread overview]
Message-ID: <20260611183708.GA222320@fedora> (raw)
In-Reply-To: <20260611110543-mutt-send-email-mst@kernel.org>
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On Thu, Jun 11, 2026 at 11:09:35AM -0400, Michael S. Tsirkin wrote:
> On Thu, Jun 11, 2026 at 04:04:20PM +0100, Peter Maydell wrote:
> > On Thu, 11 Jun 2026 at 15:46, Michael S. Tsirkin <mst@redhat.com> wrote:
> > >
> > > On Thu, Jun 11, 2026 at 10:20:22AM -0400, Stefan Hajnoczi wrote:
> > > > Gavin posted the lspci output:
> > > >
> > > > Region 0: Memory at 661ffd000000 (64-bit, prefetchable) [size=16M]
> > > > Region 2: Memory at 662000000000 (64-bit, prefetchable) [size=128G]
> > > > Region 4: Memory at 661ffe000000 (64-bit, prefetchable) [size=32M]
> > > >
> > > > These are prefetchable memory BARs, so I would expect them to be
> > > > mmappable. Why does QEMU have no way of knowing upfront whether they can
> > > > be mmapped?
> > >
> > >
> > > They can be mmapped. The issue is just that after mmap flatview uses
> > > memcpy/memmove on them, and that might not match what guest driver is
> > > expecting specifically for 1/2/4/8 byte accesses.
> >
> > Huh? The guest driver has nothing to do with it, surely.
>
> My answer is I don't know.
>
> But the commit that introduced the regression says:
>
> The assumption here is that accesses initiated by the VM are
> driven by a device specific driver, which knows the device
> capabilities.
>
> > The
> > problem is that for some PCI devices (like the network card
> > mentioned in 4a2e242bbb30's commit message) the BAR is *not*
> > safe for arbitrary access (because the actual real host hardware
> > inside it is not RAM).
>
> But we don't do arbitrary access. Why would we?
>
> > That commit disabled direct access
> > for all vfio MRs, which is safe but overcautious. Would
> > "direct access is OK if this is a prefetchable memory BAR" be OK?
> > Or do some prefetchable memory BARs still have restrictions
> > beyond those of real RAM?
I wonder the same thing.
> >
> > > Removing mmap is one solution, this is what vfio does now.
> > > Fixing flatview is another.
> >
> > No, you can't fix this in flatview. If a BAR is not safe for
> > direct access then it is not safe for direct access.
> >
> > -- PMM
>
> There's no such thing as "not safe for direct access" in PCI.
> All operations are memory operations.
> What can be unsafe is accesses of specific width and length.
>
> So we should not use variable length memcpy/memmove which
> do that. Fixes length memcpy/memmove exactly mimic what
> guest does, so they are safe.
The bounce buffer approach doesn't seem like a solution to me: if the
device has alignment and size restrictions on accesses, then the bounce
buffer won't get them right because it doesn't know where the registers
live within the BAR.
Also, the guest initiated I/O to a VIRTIO device pointing to a buffer in
another PCI device's BAR. In this case any failure to handle BAR
accesses would be the guest's problem. It cannot assume that the VIRTIO
device follows a specific DMA transfer pattern with respect to
alignment/size.
Stefan
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next prev parent reply other threads:[~2026-06-11 18:37 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-08 0:18 [PATCH RFCv1] virtio: Inherit max bounce buffer size from bus parent if possible Gavin Shan
2026-06-08 8:55 ` Daniel P. Berrangé
2026-06-08 11:11 ` Gavin Shan
2026-06-08 11:38 ` Daniel P. Berrangé
2026-06-09 2:08 ` Gavin Shan
2026-06-09 16:25 ` Peter Xu
2026-06-10 0:32 ` Gavin Shan
2026-06-10 9:54 ` Pavel Hrdina
2026-06-10 10:55 ` Gavin Shan
2026-06-10 12:12 ` Michael S. Tsirkin
2026-06-10 12:19 ` Gavin Shan
2026-06-10 12:27 ` Michael S. Tsirkin
2026-06-10 13:00 ` Gavin Shan
2026-06-10 13:54 ` Gavin Shan
2026-06-10 14:06 ` Michael S. Tsirkin
2026-06-10 15:36 ` Peter Xu
2026-06-10 16:11 ` Peter Maydell
2026-06-10 16:19 ` Michael S. Tsirkin
2026-06-10 19:10 ` Peter Xu
2026-06-10 21:03 ` Michael S. Tsirkin
2026-06-10 21:27 ` Peter Xu
2026-06-10 21:44 ` Michael S. Tsirkin
2026-06-10 16:18 ` Michael S. Tsirkin
2026-06-11 4:33 ` Gavin Shan
2026-06-11 5:31 ` Michael S. Tsirkin
2026-06-11 6:28 ` Gavin Shan
2026-06-11 6:34 ` Michael S. Tsirkin
2026-06-11 12:33 ` Gavin Shan
2026-06-11 12:48 ` Peter Maydell
2026-06-11 14:10 ` Michael S. Tsirkin
2026-06-11 14:55 ` Peter Maydell
2026-06-11 15:05 ` Michael S. Tsirkin
2026-06-11 15:25 ` Michael S. Tsirkin
2026-06-11 15:29 ` Peter Maydell
2026-06-11 15:57 ` Michael S. Tsirkin
2026-06-11 16:16 ` Peter Maydell
2026-06-11 16:42 ` Michael S. Tsirkin
2026-06-11 16:53 ` Peter Maydell
2026-06-11 17:02 ` Michael S. Tsirkin
2026-06-11 18:20 ` Peter Xu
2026-06-11 20:52 ` Michael S. Tsirkin
2026-06-11 16:13 ` Michael S. Tsirkin
2026-06-11 6:51 ` Michael S. Tsirkin
2026-06-10 12:23 ` Pavel Hrdina
2026-06-10 14:04 ` Gavin Shan
2026-06-10 14:08 ` Michael S. Tsirkin
2026-06-10 9:49 ` Michael S. Tsirkin
2026-06-10 18:30 ` Stefan Hajnoczi
2026-06-10 21:00 ` Michael S. Tsirkin
2026-06-11 14:20 ` Stefan Hajnoczi
2026-06-11 14:45 ` Michael S. Tsirkin
2026-06-11 15:04 ` Peter Maydell
2026-06-11 15:09 ` Michael S. Tsirkin
2026-06-11 18:37 ` Stefan Hajnoczi [this message]
2026-06-11 20:54 ` Michael S. Tsirkin
2026-06-11 1:19 ` Gavin Shan
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