From: Chen Pei <cp0613@linux.alibaba.com>
To: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com,
alistair.francis@wdc.com, liwei1518@gmail.com,
daniel.barboza@oss.qualcomm.com, zhiwei_liu@linux.alibaba.com,
chao.liu.zevorn@gmail.com, sunilvl@ventanamicro.com,
dave.jiang@intel.com, alison.schofield@intel.com,
imammedo@redhat.com, mst@redhat.com, guoren@kernel.org
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-cxl@vger.kernel.org
Subject: [PATCH v2 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL
Date: Thu, 18 Jun 2026 17:38:26 +0800 [thread overview]
Message-ID: <20260618093827.3507-5-cp0613@linux.alibaba.com> (raw)
In-Reply-To: <20260618093827.3507-1-cp0613@linux.alibaba.com>
Add test_acpi_riscv64_virt_tcg_cxl() to verify that enabling CXL on
the RISC-V virt machine produces correct ACPI tables, including the
ACPI0017 CXLM device with _DEP in the DSDT and the CEDT table.
The test boots with cxl=on, one pxb-cxl bus (bus_nr=12), a CXL root
port, a cxl-type3 persistent memory device, and a fixed memory window,
mirroring the existing x86 q35 CXL test pattern.
Since pxb-cxl is a root bus, using -cdrom causes QEMU to auto-plug the
cdrom drive into pxb-cxl, triggering "Only PCI/PCIe bridges can be
plugged into pxb-cxl". The ISO is instead attached explicitly via a
virtio-scsi-pci controller on pcie.0, following the same approach as
test_acpi_aarch64_virt_tcg_pxb().
Signed-off-by: Chen Pei <cp0613@linux.alibaba.com>
---
tests/data/acpi/riscv64/virt/CEDT.cxl | Bin 0 -> 108 bytes
tests/data/acpi/riscv64/virt/DSDT.cxl | Bin 0 -> 6212 bytes
tests/qtest/bios-tables-test.c | 54 ++++++++++++++++++++++++++
3 files changed, 54 insertions(+)
create mode 100644 tests/data/acpi/riscv64/virt/CEDT.cxl
create mode 100644 tests/data/acpi/riscv64/virt/DSDT.cxl
diff --git a/tests/data/acpi/riscv64/virt/CEDT.cxl b/tests/data/acpi/riscv64/virt/CEDT.cxl
new file mode 100644
index 0000000000000000000000000000000000000000..81d746dfb09ccb147e26bb64060404ca3191d097
GIT binary patch
literal 108
zc-nJzbqUE~U|?VjaPoKd2v%^42yj*a0!E-1hz+6{7!(+IKx!BefCEf2LP-snumA^?
O0aMEg#QH!C(hmS*@&^F`
literal 0
Hc-jL100001
diff --git a/tests/data/acpi/riscv64/virt/DSDT.cxl b/tests/data/acpi/riscv64/virt/DSDT.cxl
new file mode 100644
index 0000000000000000000000000000000000000000..45999636a05a16f68d1f418a58d9b80a8a62c9bd
GIT binary patch
literal 6212
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Cu_#Oc
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Hc-jL100001
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 510751799e..4625b76692 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2194,6 +2194,56 @@ static void test_acpi_riscv64_virt_tcg(void)
free_test_data(&data);
}
+#ifdef CONFIG_POSIX
+static void test_acpi_riscv64_virt_tcg_cxl(void)
+{
+ gchar *tmp_path = g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL);
+ gchar *params;
+
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * MiB,
+ .variant = ".cxl",
+ };
+
+ /*
+ * While using -cdrom, the cdrom would auto-plug into pxb-cxl because
+ * its bus is also a root bus, triggering "Only PCI/PCIe bridges can be
+ * plugged into pxb-cxl". Attach the ISO explicitly to a scsi controller
+ * on pcie.0 instead, following the same pattern as
+ * test_acpi_aarch64_virt_tcg_pxb().
+ */
+ params = g_strdup_printf("-cpu rva22s64"
+ " -machine cxl=on"
+ " -device pcie-root-port,chassis=1,id=pci.1,bus=pcie.0"
+ " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
+ " -drive file=tests/data/uefi-boot-images/"
+ "bios-tables-test.riscv64.iso.qcow2,"
+ "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
+ " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
+ "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
+ " -object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M"
+ " -object memory-backend-file,id=lsa1,mem-path=%s,size=256M"
+ " -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
+ " -device cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
+ " -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1"
+ " -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,"
+ "cxl-fmw.0.interleave-granularity=8k",
+ tmp_path, tmp_path);
+ test_acpi_one(params, &data);
+
+ g_free(params);
+ g_assert(g_rmdir(tmp_path) == 0);
+ g_free(tmp_path);
+ free_test_data(&data);
+}
+#endif /* CONFIG_POSIX */
+
static void test_acpi_aarch64_virt_tcg(void)
{
test_data data = {
@@ -2888,6 +2938,10 @@ int main(int argc, char *argv[])
test_acpi_riscv64_virt_tcg_numamem);
qtest_add_func("acpi/virt/acpispcr",
test_acpi_riscv64_virt_tcg_acpi_spcr);
+#ifdef CONFIG_POSIX
+ qtest_add_func("acpi/virt/cxl",
+ test_acpi_riscv64_virt_tcg_cxl);
+#endif
}
} else if (strcmp(arch, "loongarch64") == 0) {
if (has_tcg && qtest_has_machine("virt")) {
--
2.50.1
prev parent reply other threads:[~2026-06-18 9:38 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-18 9:38 [PATCH v2 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-06-18 9:38 ` [PATCH v2 1/4] " Chen Pei
2026-06-24 16:42 ` Daniel Henrique Barboza
2026-06-29 9:06 ` Chen Pei
2026-06-18 9:38 ` [PATCH v2 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
2026-06-18 9:38 ` [PATCH v2 3/4] hw/riscv/virt,gpex: Provide 32-bit MMIO window for CXL host bridges Chen Pei
2026-06-18 9:38 ` [PATCH v2 3/4] hw/riscv/virt, gpex: " Chen Pei
2026-06-24 17:21 ` Daniel Henrique Barboza via
2026-06-24 17:21 ` Daniel Henrique Barboza via qemu development
2026-06-24 17:21 ` [PATCH v2 3/4] hw/riscv/virt,gpex: " Daniel Henrique Barboza
2026-06-29 9:10 ` Chen Pei
2026-06-29 9:10 ` [PATCH v2 3/4] hw/riscv/virt, gpex: " Chen Pei
2026-06-18 9:38 ` Chen Pei [this message]
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