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From: Chen Pei <cp0613@linux.alibaba.com>
To: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com,
	alistair.francis@wdc.com, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,
	sunilvl@ventanamicro.com, dave.jiang@intel.com,
	alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com,
	guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 3/4] hw/riscv/virt,gpex: Provide 32-bit MMIO window for CXL host bridges
Date: Mon, 29 Jun 2026 17:10:17 +0800	[thread overview]
Message-ID: <20260629091019.71770-1-cp0613@linux.alibaba.com> (raw)
In-Reply-To: <79017627-4888-415a-9686-16367490b5b5@oss.qualcomm.com>

Hi Daniel,

On 6/24/2026 2:21 PM, Daniel Henrique Barboza wrote:
> We can get rid of the braces - it's just adding an extra identation level while
> not doing anything special. 'mmio32_size' can be declared at the start
> of create_fdt_pcie().

Makes sense. I'll move mmio32_size to the top of create_fdt_pcie() and
remove the extra braces in v3.

Thanks,
Pei

WARNING: multiple messages have this Message-ID (diff)
From: Chen Pei <cp0613@linux.alibaba.com>
To: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Cc: jic23@kernel.org, pbonzini@redhat.com, palmer@dabbelt.com,
	alistair.francis@wdc.com, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,
	sunilvl@ventanamicro.com, dave.jiang@intel.com,
	alison.schofield@intel.com, imammedo@redhat.com, mst@redhat.com,
	guoren@kernel.org, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	linux-cxl@vger.kernel.org
Subject: Re: [PATCH v2 3/4] hw/riscv/virt, gpex: Provide 32-bit MMIO window for CXL host bridges
Date: Mon, 29 Jun 2026 17:10:17 +0800	[thread overview]
Message-ID: <20260629091019.71770-1-cp0613@linux.alibaba.com> (raw)
In-Reply-To: <79017627-4888-415a-9686-16367490b5b5@oss.qualcomm.com>

Hi Daniel,

On 6/24/2026 2:21 PM, Daniel Henrique Barboza wrote:
> We can get rid of the braces - it's just adding an extra identation level while
> not doing anything special. 'mmio32_size' can be declared at the start
> of create_fdt_pcie().

Makes sense. I'll move mmio32_size to the top of create_fdt_pcie() and
remove the extra braces in v3.

Thanks,
Pei


  reply	other threads:[~2026-06-29  9:10 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-18  9:38 [PATCH v2 0/4] hw/riscv/virt: Add CXL support to the RISC-V virt machine Chen Pei
2026-06-18  9:38 ` [PATCH v2 1/4] " Chen Pei
2026-06-24 16:42   ` Daniel Henrique Barboza
2026-06-29  9:06     ` Chen Pei
2026-06-18  9:38 ` [PATCH v2 2/4] hw/riscv/virt-acpi-build: Add _DEP to ACPI0017 for CXL host bridge dependency Chen Pei
2026-06-18  9:38 ` [PATCH v2 3/4] hw/riscv/virt,gpex: Provide 32-bit MMIO window for CXL host bridges Chen Pei
2026-06-18  9:38   ` [PATCH v2 3/4] hw/riscv/virt, gpex: " Chen Pei
2026-06-24 17:21   ` [PATCH v2 3/4] hw/riscv/virt,gpex: " Daniel Henrique Barboza
2026-06-24 17:21     ` [PATCH v2 3/4] hw/riscv/virt, gpex: " Daniel Henrique Barboza via qemu development
2026-06-24 17:21     ` Daniel Henrique Barboza via
2026-06-29  9:10     ` Chen Pei [this message]
2026-06-29  9:10       ` Chen Pei
2026-06-18  9:38 ` [PATCH v2 4/4] tests/qtest: Add RISC-V ACPI bios tables test for CXL Chen Pei

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