From: sashiko-bot@kernel.org
To: "Ranjan Kumar" <ranjan.kumar@broadcom.com>
Cc: linux-scsi@vger.kernel.org
Subject: Re: [PATCH v1 02/10] mpi3mr: Update MPI Headers to revision 41
Date: Fri, 26 Jun 2026 12:07:07 +0000 [thread overview]
Message-ID: <20260626120708.32AD81F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260626114109.43685-3-ranjan.kumar@broadcom.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing endian conversion for `driver_pg1.flags` before bitwise AND.
--
commit dcead2e50e7c04fa8f12bc236d238e9408c959bb
Author: Ranjan Kumar <ranjan.kumar@broadcom.com>
mpi3mr: Update MPI Headers to revision 41
Update MPI Headers to revision 41.
> diff --git a/drivers/scsi/mpi3mr/mpi3mr_fw.c b/drivers/scsi/mpi3mr/mpi3mr_fw.c
> --- a/drivers/scsi/mpi3mr/mpi3mr_fw.c
> +++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c
[ ... ]
> @@ -4128,11 +4128,15 @@ mpi3mr_read_driver_page1(struct mpi3mr_ioc *mrioc)
> struct mpi3_driver_page1 driver_pg1;
> u16 pg_sz = sizeof(driver_pg1);
> int retval = 0;
>
> mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
> + mrioc->skip_dev_shutdown_on_unload = 0;
>
> retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
> - if (!retval && driver_pg1.time_stamp_update)
> +
> + if (retval)
> + return;
> +
> + if (driver_pg1.time_stamp_update)
> mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
> +
> + mrioc->skip_dev_shutdown_on_unload =
> + (driver_pg1.flags &
> + MPI3_DRIVER1_FLAGS_DEVICE_SHUTDOWN_ON_UNLOAD_DISABLE) ? 1 : 0;
[Severity: High]
Does this code miss an endianness conversion for driver_pg1.flags before the
bitwise AND?
If driver_pg1.flags is populated natively in little-endian format from the
controller without swapping, evaluating it against a host-endian macro could
lead to incorrect logic on Big-Endian architectures.
For example, if the firmware sets
MPI3_DRIVER1_FLAGS_DEVICE_SHUTDOWN_ON_UNLOAD_DISABLE (0x01), a Big-Endian CPU
would read it as 0x01000000, evaluate the check to false, and fail to skip the
requested device shutdown.
Conversely, if a future flag sets bit 24, a Big-Endian CPU reads it as
0x00000001, evaluates the check to true, and falsely skips device shutdown,
which could lead to data loss such as unflushed drive caches.
Is le32_to_cpu() or similar needed here?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260626114109.43685-1-ranjan.kumar@broadcom.com?part=2
next prev parent reply other threads:[~2026-06-26 12:07 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-26 11:40 [PATCH v1 00/10] mpi3mr: Few Enhancements and minor fixes Ranjan Kumar
2026-06-26 11:41 ` [PATCH v1 01/10] mpi3mr: Skip device shutdown during unload per controller configuration Ranjan Kumar
2026-06-26 12:03 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 02/10] mpi3mr: Update MPI Headers to revision 41 Ranjan Kumar
2026-06-26 12:07 ` sashiko-bot [this message]
2026-06-26 11:41 ` [PATCH v1 03/10] mpi3mr: Add early timestamp synchronization after driver load Ranjan Kumar
2026-06-26 11:41 ` [PATCH v1 04/10] mpi3mr: Fix NVMe page size caching for non-operational devices Ranjan Kumar
2026-06-26 12:07 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 05/10] mpi3mr: Fix performance regression caused by extended IRQ poll sleep Ranjan Kumar
2026-06-26 12:02 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 06/10] mpi3mr: Fix memory leak on operational queue creation failure Ranjan Kumar
2026-06-26 12:02 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 07/10] mpi3mr: Fix firmware event reference leak during cleanup Ranjan Kumar
2026-06-26 12:03 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 08/10] mpi3mr: Fix SAS port allocation and registration error handling Ranjan Kumar
2026-06-26 12:06 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 09/10] mpi3mr: Fix SAS PHY cleanup in host addition error paths Ranjan Kumar
2026-06-26 12:16 ` sashiko-bot
2026-06-26 11:41 ` [PATCH v1 10/10] mpi3mr: Driver version update to 8.18.0.8.50 Ranjan Kumar
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