* [PULL 2/7] Revert "hw/ppc: Deprecate 405 CPUs"
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
@ 2026-07-03 4:43 ` Harsh Prateek Bora
2026-07-03 4:43 ` [PULL 3/7] hw/pci-host: Split PowerNV PHB5 code from PHB4 files Harsh Prateek Bora
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Glenn Miles, Cédric Le Goater
From: Glenn Miles <milesg@linux.ibm.com>
This reverts commit 52f0b59ec6b780f2a3e162d5862b90b406fa4697.
The PowerPC 405 CPU is used by the PPE42 CPU which was added to
QEMU v10.2. The PPE42 CPU is basically a stripped down version
of the PowerPC 405 CPU and is used by the Power9, Power10, and
Power11 CPUs as an embedded processor to handle various tasks.
Also, IBM has plans to use the PowerPC 405 CPU model within a
year to model the On Chip Controller (OCC), which has an embedded
PPC405 CPU. Therefore, this patch removes the PowerPC 405 CPU
from the deprecated list.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
Acked-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260505144621.1308457-1-milesg@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
docs/about/deprecated.rst | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index cf3e1a007c..169c5dfe4f 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -206,15 +206,6 @@ in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and
but for consistency these will get removed in a future release, too.
Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead.
-PPC 405 CPUs (since 10.0)
-'''''''''''''''''''''''''
-
-The PPC 405 CPU has no known users and the ``ref405ep`` machine was
-removed in QEMU 10.0. Since the IBM POWER [8-11] processors uses an
-embedded 405 for power management (OCC) and other internal tasks, it
-is theoretically possible to use QEMU to model them. Let's keep the
-CPU implementation for a while before removing all support.
-
Power8E and Power8NVL CPUs and corresponding Pnv chips (since 10.1)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 3/7] hw/pci-host: Split PowerNV PHB5 code from PHB4 files
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
2026-07-03 4:43 ` [PULL 2/7] Revert "hw/ppc: Deprecate 405 CPUs" Harsh Prateek Bora
@ 2026-07-03 4:43 ` Harsh Prateek Bora
2026-07-03 4:43 ` [PULL 4/7] target/ppc: Expose the TB offset of the guest in QEMU monitor Harsh Prateek Bora
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Jishnu Warrier, Aditya Gupta
From: Jishnu Warrier <jishnuvw@linux.ibm.com>
Separate Power10/11 PHB5 implementation from Power9 PHB4 code for
better maintainability and clarity. This is a pure code movement
with no functional changes.
Signed-off-by: Jishnu Warrier <jishnuvw@linux.ibm.com>
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260608093430.2729688-1-jishnuvw@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
hw/pci-host/pnv_phb4.c | 6 ---
hw/pci-host/pnv_phb4_pec.c | 58 ----------------------------
hw/pci-host/pnv_phb5.c | 23 ++++++++++++
hw/pci-host/pnv_phb5_pec.c | 77 ++++++++++++++++++++++++++++++++++++++
hw/pci-host/meson.build | 2 +
5 files changed, 102 insertions(+), 64 deletions(-)
create mode 100644 hw/pci-host/pnv_phb5.c
create mode 100644 hw/pci-host/pnv_phb5_pec.c
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 396bc47817..705a5bcf07 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1721,11 +1721,6 @@ static const TypeInfo pnv_phb4_type_info = {
}
};
-static const TypeInfo pnv_phb5_type_info = {
- .name = TYPE_PNV_PHB5,
- .parent = TYPE_PNV_PHB4,
- .instance_size = sizeof(PnvPHB4),
-};
static void pnv_phb4_root_bus_get_prop(Object *obj, Visitor *v,
const char *name,
@@ -1794,7 +1789,6 @@ static void pnv_phb4_register_types(void)
{
type_register_static(&pnv_phb4_root_bus_info);
type_register_static(&pnv_phb4_type_info);
- type_register_static(&pnv_phb5_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);
}
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 58ec14ec2f..ee5cdc3e45 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -394,67 +394,9 @@ static const TypeInfo pnv_pec_type_info = {
}
};
-/*
- * POWER10 definitions
- */
-static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
-{
- return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
-}
-
-static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
-{
- return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
-}
-
-static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
-{
- /* index goes down ... */
- return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
-}
-
-/*
- * PEC0 -> 3 stacks
- * PEC1 -> 3 stacks
- */
-static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
-
-static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
-{
- PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
- static const char compat[] = "ibm,power10-pbcq";
- static const char stk_compat[] = "ibm,power10-phb-stack";
-
- pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
- pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
- pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
- pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
- pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
- pecc->compat = compat;
- pecc->compat_size = sizeof(compat);
- pecc->stk_compat = stk_compat;
- pecc->stk_compat_size = sizeof(stk_compat);
- pecc->version = PNV_PHB5_VERSION;
- pecc->phb_type = TYPE_PNV_PHB5;
- pecc->num_phbs = pnv_phb5_pec_num_stacks;
-}
-
-static const TypeInfo pnv_phb5_pec_type_info = {
- .name = TYPE_PNV_PHB5_PEC,
- .parent = TYPE_PNV_PHB4_PEC,
- .instance_size = sizeof(PnvPhb4PecState),
- .class_init = pnv_phb5_pec_class_init,
- .class_size = sizeof(PnvPhb4PecClass),
- .interfaces = (const InterfaceInfo[]) {
- { TYPE_PNV_XSCOM_INTERFACE },
- { }
- }
-};
-
static void pnv_pec_register_types(void)
{
type_register_static(&pnv_pec_type_info);
- type_register_static(&pnv_phb5_pec_type_info);
}
type_init(pnv_pec_register_types);
diff --git a/hw/pci-host/pnv_phb5.c b/hw/pci-host/pnv_phb5.c
new file mode 100644
index 0000000000..c3f2e16ce6
--- /dev/null
+++ b/hw/pci-host/pnv_phb5.c
@@ -0,0 +1,23 @@
+/*
+ * QEMU PowerPC PowerNV (POWER10) PHB5 model
+ *
+ * Copyright (c) 2018-2026, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci-host/pnv_phb4.h"
+
+static const TypeInfo pnv_phb5_type_info = {
+ .name = TYPE_PNV_PHB5,
+ .parent = TYPE_PNV_PHB4,
+ .instance_size = sizeof(PnvPHB4),
+};
+
+static void pnv_phb5_register_types(void)
+{
+ type_register_static(&pnv_phb5_type_info);
+}
+
+type_init(pnv_phb5_register_types);
diff --git a/hw/pci-host/pnv_phb5_pec.c b/hw/pci-host/pnv_phb5_pec.c
new file mode 100644
index 0000000000..488ccbfb12
--- /dev/null
+++ b/hw/pci-host/pnv_phb5_pec.c
@@ -0,0 +1,77 @@
+/*
+ * QEMU PowerPC PowerNV (POWER10) PHB5 PEC model
+ *
+ * Copyright (c) 2018-2026, IBM Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_xscom.h"
+
+#define XPEC_PCI_CPLT_OFFSET 0x1000000ULL
+
+/*
+ * POWER10 definitions
+ */
+static uint32_t pnv_phb5_pec_xscom_cplt_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_NEST_CPLT_BASE + XPEC_PCI_CPLT_OFFSET * pec->index;
+}
+
+static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
+}
+
+static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
+{
+ /* index goes down ... */
+ return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
+}
+
+/*
+ * PEC0 -> 3 stacks
+ * PEC1 -> 3 stacks
+ */
+static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
+
+static void pnv_phb5_pec_class_init(ObjectClass *klass, const void *data)
+{
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
+ static const char compat[] = "ibm,power10-pbcq";
+ static const char stk_compat[] = "ibm,power10-phb-stack";
+
+ pecc->xscom_cplt_base = pnv_phb5_pec_xscom_cplt_base;
+ pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
+ pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
+ pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
+ pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
+ pecc->compat = compat;
+ pecc->compat_size = sizeof(compat);
+ pecc->stk_compat = stk_compat;
+ pecc->stk_compat_size = sizeof(stk_compat);
+ pecc->version = PNV_PHB5_VERSION;
+ pecc->phb_type = TYPE_PNV_PHB5;
+ pecc->num_phbs = pnv_phb5_pec_num_stacks;
+}
+
+static const TypeInfo pnv_phb5_pec_type_info = {
+ .name = TYPE_PNV_PHB5_PEC,
+ .parent = TYPE_PNV_PHB4_PEC,
+ .instance_size = sizeof(PnvPhb4PecState),
+ .class_init = pnv_phb5_pec_class_init,
+ .class_size = sizeof(PnvPhb4PecClass),
+ .interfaces = (const InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_phb5_pec_register_types(void)
+{
+ type_register_static(&pnv_phb5_pec_type_info);
+}
+
+type_init(pnv_phb5_pec_register_types);
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 86b754d0b0..3217e7e912 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -44,5 +44,7 @@ specific_ss.add(when: 'CONFIG_PCI_POWERNV', if_true: files(
'pnv_phb3_pbcq.c',
'pnv_phb4.c',
'pnv_phb4_pec.c',
+ 'pnv_phb5.c',
+ 'pnv_phb5_pec.c',
'pnv_phb.c',
))
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 4/7] target/ppc: Expose the TB offset of the guest in QEMU monitor
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
2026-07-03 4:43 ` [PULL 2/7] Revert "hw/ppc: Deprecate 405 CPUs" Harsh Prateek Bora
2026-07-03 4:43 ` [PULL 3/7] hw/pci-host: Split PowerNV PHB5 code from PHB4 files Harsh Prateek Bora
@ 2026-07-03 4:43 ` Harsh Prateek Bora
2026-07-03 4:44 ` [PULL 5/7] docs/system/ppc/pseries: Update the link to the SLOF repository Harsh Prateek Bora
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:43 UTC (permalink / raw)
To: qemu-devel
Cc: Gautam Menghani, Amit Machhiwal, Vaibhav Jain, Sneh Shikha Yadav
From: Gautam Menghani <gautam@linux.ibm.com>
When debugging issues in KVM guests, it is sometimes helpful to have a
unified trace log of both guest and host to see where things are going
wrong. Expose the TB (timebase) offset through QEMU monitor to enable
capturing of unified log.
The below steps can be then used for KVM guests to get a unified log:
1. In host
trace-cmd record -e kvm_hv:kvm_guest_enter -e kvm_hv:kvm_guest_exit \
-C ppc-tb -o trace_host.dat
2. In guest
trace-cmd record -e powerpc:hcall_entry -e powerpc:hcall_exit -C ppc-tb \
--ts-offset <TB offset from QEMU monitor> -o trace_guest.dat
NOTE: The TB offset would be reported as a negative number in QEMU
monitor. For this step, the minus sign must be ignored.
3. Transfer the guest logs to the host with scp/rsync
4. Unify the logs
trace-cmd report -i trace_host.dat -i trace_guest.dat > combined_log
In case of TCG guests, the TB offset would be
reported as 0 since the offset logic is not applicable in this case.
Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Reviewed-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Signed-off-by: Gautam Menghani <gautam@linux.ibm.com>
Tested-by: Sneh Shikha Yadav <syadav@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260629052602.78276-1-gautam@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
target/ppc/cpu.h | 1 +
hw/ppc/ppc.c | 5 +++++
target/ppc/cpu_init.c | 5 +++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 057c54bbb8..cbd5964b1a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1693,6 +1693,7 @@ void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
uint64_t cpu_ppc_load_purr(CPUPPCState *env);
void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
+int64_t cpu_ppc_load_tb_offset(CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
target_ulong load_40x_pit(CPUPPCState *env);
void store_40x_pit(CPUPPCState *env, target_ulong val);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index a512d4fa64..b123b4cc1c 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -515,6 +515,11 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset;
}
+int64_t cpu_ppc_load_tb_offset(CPUPPCState *env)
+{
+ return env->tb_env->tb_offset;
+}
+
uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
{
ppc_tb_t *tb_env = env->tb_env;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index a02187ce5a..8cab5e12b6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7620,8 +7620,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#if !defined(CONFIG_USER_ONLY)
if (env->tb_env) {
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
- " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
- cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
+ " DECR " TARGET_FMT_lu " TB_OFFSET %016" PRId64 "\n",
+ cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env),
+ cpu_ppc_load_decr(env), cpu_ppc_load_tb_offset(env));
}
#else
qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 5/7] docs/system/ppc/pseries: Update the link to the SLOF repository
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
` (2 preceding siblings ...)
2026-07-03 4:43 ` [PULL 4/7] target/ppc: Expose the TB offset of the guest in QEMU monitor Harsh Prateek Bora
@ 2026-07-03 4:44 ` Harsh Prateek Bora
2026-07-03 4:44 ` [PULL 6/7] ppc/pnv: avoid regenerating DTB if external DTB is present Harsh Prateek Bora
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Thomas Huth, Daniel P. Berrangé
From: Thomas Huth <th.huth@posteo.eu>
SLOF has been moved to gitlab.com already a while ago. We updated
the link in pc-bios/README in commit 7f98b4f25ed9 ("pseries: Update
SLOF firmware image"), but forgot to update it in the manual, too.
Signed-off-by: Thomas Huth <th.huth@posteo.eu>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20260702074842.4806-1-th.huth@posteo.eu
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
docs/system/ppc/pseries.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index bbc51aa7fc..107091a37f 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/system/ppc/pseries.rst
@@ -43,7 +43,7 @@ Firmware
The pSeries platform in QEMU comes with 2 firmwares:
-`SLOF <https://github.com/aik/SLOF>`_ (Slimline Open Firmware) is an
+`SLOF <https://gitlab.com/slof/slof>`_ (Slimline Open Firmware) is an
implementation of the `IEEE 1275-1994, Standard for Boot (Initialization
Configuration) Firmware: Core Requirements and Practices
<https://standards.ieee.org/standard/1275-1994.html>`_.
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 6/7] ppc/pnv: avoid regenerating DTB if external DTB is present
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
` (3 preceding siblings ...)
2026-07-03 4:44 ` [PULL 5/7] docs/system/ppc/pseries: Update the link to the SLOF repository Harsh Prateek Bora
@ 2026-07-03 4:44 ` Harsh Prateek Bora
2026-07-03 4:44 ` [PULL 7/7] ppc/pnv: add test to verify external DTB is honored Harsh Prateek Bora
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Shivang Upadhyay, Aditya Gupta, Amit Machhiwal
From: Shivang Upadhyay <shivangu@linux.ibm.com>
Currently externally provided dtb is overwritten in `pnv_reset`.
Fix this by only creating dtb if not provided from `-dtb`.
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com>
Reviewed-by: Amit Machhiwal <amachhiw@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260630103508.254000-2-shivangu@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
hw/ppc/pnv.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 62812f22f8..afb6019b10 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -803,9 +803,13 @@ static void pnv_reset(MachineState *machine, ResetType type)
mpipl_write_succeeded = do_mpipl_write(pnv);
}
- /* Regenerate device tree */
- fdt = pnv_dt_create(machine);
- _FDT((fdt_pack(fdt)));
+ /* Only create new dt if not provided in -dtb */
+ if (!machine->dtb) {
+ fdt = pnv_dt_create(machine);
+ _FDT((fdt_pack(fdt)));
+ } else {
+ fdt = machine->fdt;
+ }
/*
* If it's a MPIPL boot, add the "mpipl-boot" property, and reset the
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PULL 7/7] ppc/pnv: add test to verify external DTB is honored
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
` (4 preceding siblings ...)
2026-07-03 4:44 ` [PULL 6/7] ppc/pnv: avoid regenerating DTB if external DTB is present Harsh Prateek Bora
@ 2026-07-03 4:44 ` Harsh Prateek Bora
2026-07-03 4:57 ` [PULL 0/7] ppc queue Harsh Prateek Bora
2026-07-05 17:57 ` Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:44 UTC (permalink / raw)
To: qemu-devel; +Cc: Shivang Upadhyay, Aditya Gupta
From: Shivang Upadhyay <shivangu@linux.ibm.com>
Test boots a powernv11 machine, using a custom dtb.
Custom dtb has the following bootargs.
chosen {
bootargs = "hello world";
};
Test Checks whether above bootargs make it to kernel's command line.
Reviewed-by: Aditya Gupta <adityag@linux.ibm.com>
Signed-off-by: Shivang Upadhyay <shivangu@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260630103508.254000-3-shivangu@linux.ibm.com
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
---
tests/functional/ppc64/test_powernv.py | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/tests/functional/ppc64/test_powernv.py b/tests/functional/ppc64/test_powernv.py
index 0ea6c93e42..b5b2f0d158 100755
--- a/tests/functional/ppc64/test_powernv.py
+++ b/tests/functional/ppc64/test_powernv.py
@@ -27,6 +27,11 @@ class PowernvMachine(LinuxKernelTest):
'buildroot/qemu_ppc64le_powernv8-2025.02/rootfs.ext2'),
'aee2192b692077c4bde31cb56ce474424b358f17cec323d5c94af3970c9aada2')
+ # testdtb for power11, which contains string "hello world" in command line
+ ASSET_SAMPLE_DTB = Asset(
+ ('https://github.com/roz3x/qemu/raw/refs/heads/sample-dtb/qemu-powernv11.dtb'),
+ 'ea1271516264eea1eb58a067a99d0c2ca9528be8dc7d4e46bb2d5ae0d42fc568')
+
def do_test_linux_boot(self, command_line = KERNEL_COMMON_COMMAND_LINE):
self.require_accelerator("tcg")
kernel_path = self.ASSET_KERNEL.fetch()
@@ -104,6 +109,20 @@ def do_test_ppc64_powernv(self, proc):
# Device detection output driven by udev probing is sometimes cut off
# from console output, suspect S14silence-console init script.
+ def test_ppc64_powernv_external_dtb(self):
+ self.set_machine('powernv11')
+ self.require_accelerator("tcg")
+
+ kernel_path = self.ASSET_KERNEL.fetch()
+ sample_dtb_path = self.ASSET_SAMPLE_DTB.fetch()
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', sample_dtb_path)
+ self.vm.launch()
+
+ # check if custom dtb is reflected or not
+ wait_for_console_pattern(self, "Kernel command line: hello world", self.panic_message)
+
def test_powernv8(self):
self.set_machine('powernv8')
self.do_test_ppc64_powernv('P8')
--
2.52.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PULL 0/7] ppc queue
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
` (5 preceding siblings ...)
2026-07-03 4:44 ` [PULL 7/7] ppc/pnv: add test to verify external DTB is honored Harsh Prateek Bora
@ 2026-07-03 4:57 ` Harsh Prateek Bora
2026-07-05 17:57 ` Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Harsh Prateek Bora @ 2026-07-03 4:57 UTC (permalink / raw)
To: stefanha, stefanha, qemu-devel
Hi Stefan,
I had ran the gitlab CI here:
https://gitlab.com/harshpb/qemu/-/pipelines/2646372305
Checkpatch error for line length exceeding can be ignored.
Other failure (migration-compat-aarch64) seems to exist in baseline.
Thanks
Harsh
On 03/07/26 10:13 am, Harsh Prateek Bora wrote:
> The following changes since commit b4bdad7dcef623d2874df4e79e0be01075096c3b:
>
> Merge tag 'dump-pr-v1' of https://gitlab.com/marcandre.lureau/qemu into staging (2026-07-02 16:04:08 +0200)
>
> are available in the Git repository at:
>
> https://gitlab.com/harshpb/qemu.git tags/pull-ppc-for-11.1-misc-20260703
>
> for you to fetch changes up to f9d05801eb4acd6402d73cb25d498a2419920cf9:
>
> ppc/pnv: add test to verify external DTB is honored (2026-07-03 10:07:21 +0530)
>
> ----------------------------------------------------------------
> PPC queue for 2026-07-03
> * SLOF FW update to 20260627
> * ppc/pnv: external dtb fix and test addition
> * PHB code refactor for better maintainability
> * Revert deprecation of 405 CPUs
> * target/ppc: Expose TB offset of guest in Qemu monitor
>
> -----BEGIN PGP SIGNATURE-----
>
> iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmpHPNAACgkQRUTplPnW
> j7tkjQ/9FP3/sTw0MxhGdLItxurrEzu3f4jiDKpnjEIqiJInzYl/2fJKZU611PSp
> gydfdNhkr71TxuJggibAosEblcWRq9KqQXysDpNrJ8rqEIeLj0lv9/JigLTZqU3e
> vsfDmfdCAB7YTtpm6HkTYW81EPD0X8AwQqz4FCNDQ0zeNUBIU8IU/ARP2j80CTnm
> 5xRK42aZb9CMYYIk3p8l4FuZmv6Y0Jf0daXM4WsEdHu9KjGvYr1glTY/lgblNPug
> kWIcjPqQ6x/hloYqxTTcsfJBnKfdaVppuh6LbJbgISsQIBzTqrD2HvEIpNFJRKnS
> 1XGwLj6cMmm4u2tv3BF0yVDJCEff312n2VFskmOrCUJOR+g2UqDzMb4+7JOpufEn
> Fla38+a9H9ThdnUNaak8+KquHDOJzDAOugOdMvsID8KlJ/q3wrTTEUUImj5Bwyqz
> Gc7naNx+3D+BSiahDe4LP71ZFLrQJ/eYCj71for5xZNcZVOQ6IDhymEMUAcRzkt6
> 2qICF6XmkYfuH+1113KMxG65NpKGEvktONQ6UpLWTubQ++BNK1Bt2v8PAWSis/d8
> EYg5M/R7RqhbxufIUDLXJIuxB3xuiVg+e+x/M8X0LffmYhPI1cuZPmth4/75IKL+
> 9Vddgc1hSHX1EUjRyZpoK6WArOTNvUOZMEcAhGr/0NgK5O/1Z10=
> =1TRv
> -----END PGP SIGNATURE-----
>
> ----------------------------------------------------------------
> Gautam Menghani (1):
> target/ppc: Expose the TB offset of the guest in QEMU monitor
>
> Glenn Miles (1):
> Revert "hw/ppc: Deprecate 405 CPUs"
>
> Jishnu Warrier (1):
> hw/pci-host: Split PowerNV PHB5 code from PHB4 files
>
> Shivang Upadhyay (2):
> ppc/pnv: avoid regenerating DTB if external DTB is present
> ppc/pnv: add test to verify external DTB is honored
>
> Thomas Huth (2):
> pseries: Update SLOF firmware image to release 20260627
> docs/system/ppc/pseries: Update the link to the SLOF repository
>
> docs/about/deprecated.rst | 9 ----
> docs/system/ppc/pseries.rst | 2 +-
> target/ppc/cpu.h | 1 +
> hw/pci-host/pnv_phb4.c | 6 ---
> hw/pci-host/pnv_phb4_pec.c | 58 -------------------------
> hw/pci-host/pnv_phb5.c | 23 ++++++++++
> hw/pci-host/pnv_phb5_pec.c | 77 +++++++++++++++++++++++++++++++++
> hw/ppc/pnv.c | 10 +++--
> hw/ppc/ppc.c | 5 +++
> target/ppc/cpu_init.c | 5 ++-
> hw/pci-host/meson.build | 2 +
> pc-bios/README | 2 +-
> pc-bios/slof.bin | Bin 994176 -> 997576 bytes
> roms/SLOF | 2 +-
> tests/functional/ppc64/test_powernv.py | 19 ++++++++
> 15 files changed, 140 insertions(+), 81 deletions(-)
> create mode 100644 hw/pci-host/pnv_phb5.c
> create mode 100644 hw/pci-host/pnv_phb5_pec.c
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PULL 0/7] ppc queue
2026-07-03 4:43 [PULL 0/7] ppc queue Harsh Prateek Bora
` (6 preceding siblings ...)
2026-07-03 4:57 ` [PULL 0/7] ppc queue Harsh Prateek Bora
@ 2026-07-05 17:57 ` Stefan Hajnoczi
7 siblings, 0 replies; 9+ messages in thread
From: Stefan Hajnoczi @ 2026-07-05 17:57 UTC (permalink / raw)
To: Harsh Prateek Bora; +Cc: qemu-devel
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.
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^ permalink raw reply [flat|nested] 9+ messages in thread