From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Subject: [PULL 09/23] target/mips: add Octeon SMS4 COP2 helpers
Date: Tue, 7 Jul 2026 20:15:14 +0200 [thread overview]
Message-ID: <20260707181529.60191-10-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260707181529.60191-1-philmd@oss.qualcomm.com>
From: James Hilliard <james.hilliard1@gmail.com>
Add helper support for the Octeon SMS4 operation selectors. SMS4 reuses
the AES RESINP, IV, and key banks, so the helpers share the existing AES
state while implementing the SMS4 ECB/CBC encrypt and decrypt operations.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-9-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/mips/helper.h | 4 ++
target/mips/tcg/octeon_crypto.c | 123 ++++++++++++++++++++++++++++++++
2 files changed, 127 insertions(+)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 39c226ded92..4949b94657f 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -56,6 +56,10 @@ DEF_HELPER_2(octeon_cp2_mt_aes_enc_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_enc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_dec_cbc1, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_aes_dec1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_sms4_enc_cbc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_sms4_enc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_sms4_dec_cbc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_sms4_dec1, void, env, i64)
/* microMIPS functions */
DEF_HELPER_4(lwm, void, env, tl, tl, i32)
diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c
index 117e3a5026e..bcffd17ab6c 100644
--- a/target/mips/tcg/octeon_crypto.c
+++ b/target/mips/tcg/octeon_crypto.c
@@ -985,6 +985,129 @@ void helper_octeon_cp2_mt_aes_dec1(CPUMIPSState *env, uint64_t value)
octeon_aes_decrypt_common(crypto, false);
}
+static uint32_t octeon_sms4_t(uint32_t x)
+{
+ x = sm4_subword(x);
+ return x ^ rol32(x, 2) ^ rol32(x, 10) ^ rol32(x, 18) ^ rol32(x, 24);
+}
+
+static uint32_t octeon_sms4_t_key(uint32_t x)
+{
+ x = sm4_subword(x);
+ return x ^ rol32(x, 13) ^ rol32(x, 23);
+}
+
+static void octeon_sms4_expand_key(const uint8_t *key, uint32_t round_keys[32])
+{
+ static const uint32_t fk[4] = {
+ 0xa3b1bac6U, 0x56aa3350U, 0x677d9197U, 0xb27022dcU,
+ };
+ uint32_t k[36];
+
+ for (int i = 0; i < 4; i++) {
+ k[i] = ldl_be_p(key + i * 4) ^ fk[i];
+ }
+ for (int i = 0; i < 32; i++) {
+ k[i + 4] = k[i] ^ octeon_sms4_t_key(k[i + 1] ^ k[i + 2] ^
+ k[i + 3] ^ sm4_ck[i]);
+ round_keys[i] = k[i + 4];
+ }
+}
+
+static void octeon_sms4_crypt_block(const uint8_t *in, uint8_t *out,
+ const uint32_t round_keys[32],
+ bool encrypt)
+{
+ uint32_t x[36];
+
+ for (int i = 0; i < 4; i++) {
+ x[i] = ldl_be_p(in + i * 4);
+ }
+ for (int i = 0; i < 32; i++) {
+ uint32_t rk = round_keys[encrypt ? i : 31 - i];
+
+ x[i + 4] = x[i] ^ octeon_sms4_t(x[i + 1] ^ x[i + 2] ^
+ x[i + 3] ^ rk);
+ }
+ stl_be_p(out, x[35]);
+ stl_be_p(out + 4, x[34]);
+ stl_be_p(out + 8, x[33]);
+ stl_be_p(out + 12, x[32]);
+}
+
+static void octeon_sms4_crypt_common(MIPSOcteonCryptoState *crypto,
+ bool encrypt, bool cbc)
+{
+ uint8_t key[16];
+ uint8_t in[16];
+ uint8_t out[16];
+ uint8_t iv[16];
+ uint8_t next_iv[16];
+ uint32_t round_keys[32];
+
+ /*
+ * SMS4 aliases the AES state onto the RESINP, IV, and KEY banks,
+ * with only the operation selectors remaining distinct.
+ */
+ octeon_aes_load_key(crypto, key, sizeof(key));
+ octeon_aes_load_block(crypto->aes_resinp, in);
+ if (cbc) {
+ octeon_aes_load_block(crypto->aes_iv, iv);
+ if (encrypt) {
+ for (int i = 0; i < sizeof(in); i++) {
+ in[i] ^= iv[i];
+ }
+ } else {
+ memcpy(next_iv, in, sizeof(next_iv));
+ }
+ }
+
+ octeon_sms4_expand_key(key, round_keys);
+ octeon_sms4_crypt_block(in, out, round_keys, encrypt);
+ if (cbc && !encrypt) {
+ for (int i = 0; i < sizeof(out); i++) {
+ out[i] ^= iv[i];
+ }
+ }
+
+ octeon_aes_store_block(crypto->aes_resinp, out);
+ if (cbc) {
+ octeon_aes_store_block(crypto->aes_iv, encrypt ? out : next_iv);
+ }
+}
+
+void helper_octeon_cp2_mt_sms4_enc_cbc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_sms4_crypt_common(crypto, true, true);
+}
+
+void helper_octeon_cp2_mt_sms4_enc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_sms4_crypt_common(crypto, true, false);
+}
+
+void helper_octeon_cp2_mt_sms4_dec_cbc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_sms4_crypt_common(crypto, false, true);
+}
+
+void helper_octeon_cp2_mt_sms4_dec1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_sms4_crypt_common(crypto, false, false);
+}
+
void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value)
{
octeon_snow3g_start(&env->octeon_crypto, value);
--
2.53.0
next prev parent reply other threads:[~2026-07-07 18:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 18:15 [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 01/23] target/mips: add Octeon COP2 crypto state Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 02/23] target/mips: add Octeon COP2 crypto helper plumbing Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 03/23] target/mips: add Octeon CRC COP2 helpers Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 04/23] target/mips: add Octeon GFM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 05/23] target/mips: add Octeon SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 06/23] target/mips: add Octeon ZUC " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 07/23] target/mips: add Octeon SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 08/23] target/mips: add Octeon AES " Philippe Mathieu-Daudé
2026-07-07 18:15 ` Philippe Mathieu-Daudé [this message]
2026-07-07 18:15 ` [PULL 10/23] target/mips: add Octeon 3DES and KASUMI " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 11/23] target/mips: add Octeon Camellia " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 12/23] target/mips: add Octeon HSH " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 13/23] target/mips: add Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 14/23] target/mips: decode Octeon COP2 register selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 15/23] target/mips: decode Octeon CRC and GFM COP2 selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 16/23] target/mips: decode Octeon HSH and SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 17/23] target/mips: decode Octeon ZUC and SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 18/23] target/mips: decode Octeon block-cipher " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 19/23] target/mips: decode Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 20/23] target/mips: add Octeon CvmCount RDHWR support Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 21/23] tests/tcg/mips: cover Octeon QMAC instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 22/23] target/sh4: fixup tcg for sh4 fipr/ftrv instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 23/23] qemu-options: Do not list -enable-kvm on MIPS binaries Philippe Mathieu-Daudé
2026-07-08 5:19 ` [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-08 15:32 ` Stefan Hajnoczi
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