From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Subject: [PULL 08/23] target/mips: add Octeon AES COP2 helpers
Date: Tue, 7 Jul 2026 20:15:13 +0200 [thread overview]
Message-ID: <20260707181529.60191-9-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260707181529.60191-1-philmd@oss.qualcomm.com>
From: James Hilliard <james.hilliard1@gmail.com>
Add helper support for the Octeon AES operation selectors. Direct
register-transfer selectors do not need helpers; the ECB/CBC encrypt and
decrypt operations consume the AES input, key, IV, and key-length state.
AESRESINP is modeled as one architectural register bank; operation
helpers consume the current AESRESINP block and write the result back to
the same bank.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-8-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/mips/helper.h | 4 +
target/mips/tcg/octeon_crypto.c | 145 ++++++++++++++++++++++++++++++++
2 files changed, 149 insertions(+)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index c4e7693df63..39c226ded92 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -52,6 +52,10 @@ DEF_HELPER_2(octeon_cp2_mt_zuc_start, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_zuc_more, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_snow3g_start, void, env, i64)
DEF_HELPER_2(octeon_cp2_mt_snow3g_more, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_aes_enc_cbc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_aes_enc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_aes_dec_cbc1, void, env, i64)
+DEF_HELPER_2(octeon_cp2_mt_aes_dec1, void, env, i64)
/* microMIPS functions */
DEF_HELPER_4(lwm, void, env, tl, tl, i32)
diff --git a/target/mips/tcg/octeon_crypto.c b/target/mips/tcg/octeon_crypto.c
index 930a67346ef..117e3a5026e 100644
--- a/target/mips/tcg/octeon_crypto.c
+++ b/target/mips/tcg/octeon_crypto.c
@@ -840,6 +840,151 @@ static void octeon_snow3g_more(MIPSOcteonCryptoState *crypto)
octeon_snow3g_queue_result(crypto);
}
+static int octeon_aes_key_bits(const MIPSOcteonCryptoState *crypto)
+{
+ enum {
+ OCTEON_AES_KEYLEN_128 = 1,
+ OCTEON_AES_KEYLEN_192 = 2,
+ OCTEON_AES_KEYLEN_256 = 3,
+ };
+
+ switch (crypto->aes_keylen) {
+ case OCTEON_AES_KEYLEN_128:
+ return 128;
+ case OCTEON_AES_KEYLEN_192:
+ return 192;
+ case OCTEON_AES_KEYLEN_256:
+ return 256;
+ default:
+ return 0;
+ }
+}
+
+static void octeon_aes_load_key(const MIPSOcteonCryptoState *crypto,
+ uint8_t *key, size_t keylen)
+{
+ stq_be_p(key, crypto->aes_key[0]);
+ stq_be_p(key + 8, crypto->aes_key[1]);
+ if (keylen > 16) {
+ stq_be_p(key + 16, crypto->aes_key[2]);
+ }
+ if (keylen > 24) {
+ stq_be_p(key + 24, crypto->aes_key[3]);
+ }
+}
+
+static void octeon_aes_load_block(const uint64_t regs[2], uint8_t *block)
+{
+ stq_be_p(block, regs[0]);
+ stq_be_p(block + 8, regs[1]);
+}
+
+static void octeon_aes_store_block(uint64_t regs[2], const uint8_t *block)
+{
+ regs[0] = ldq_be_p(block);
+ regs[1] = ldq_be_p(block + 8);
+}
+
+static void octeon_aes_encrypt_common(MIPSOcteonCryptoState *crypto, bool cbc)
+{
+ AES_KEY key;
+ uint8_t in[16];
+ uint8_t out[16];
+ uint8_t iv[16];
+ uint8_t raw_key[32] = {};
+ int bits = octeon_aes_key_bits(crypto);
+
+ if (!bits) {
+ return;
+ }
+
+ octeon_aes_load_key(crypto, raw_key, bits / 8);
+ octeon_aes_load_block(crypto->aes_resinp, in);
+ if (cbc) {
+ int i;
+
+ octeon_aes_load_block(crypto->aes_iv, iv);
+ for (i = 0; i < sizeof(in); i++) {
+ in[i] ^= iv[i];
+ }
+ }
+
+ AES_set_encrypt_key(raw_key, bits, &key);
+ AES_encrypt(in, out, &key);
+ octeon_aes_store_block(crypto->aes_resinp, out);
+ if (cbc) {
+ octeon_aes_store_block(crypto->aes_iv, out);
+ }
+}
+
+static void octeon_aes_decrypt_common(MIPSOcteonCryptoState *crypto, bool cbc)
+{
+ AES_KEY key;
+ uint8_t in[16];
+ uint8_t out[16];
+ uint8_t iv[16];
+ uint8_t next_iv[16];
+ uint8_t raw_key[32] = {};
+ int bits = octeon_aes_key_bits(crypto);
+ int i;
+
+ if (!bits) {
+ return;
+ }
+
+ octeon_aes_load_key(crypto, raw_key, bits / 8);
+ octeon_aes_load_block(crypto->aes_resinp, in);
+ if (cbc) {
+ memcpy(next_iv, in, sizeof(next_iv));
+ octeon_aes_load_block(crypto->aes_iv, iv);
+ }
+
+ AES_set_decrypt_key(raw_key, bits, &key);
+ AES_decrypt(in, out, &key);
+ if (cbc) {
+ for (i = 0; i < sizeof(out); i++) {
+ out[i] ^= iv[i];
+ }
+ }
+
+ octeon_aes_store_block(crypto->aes_resinp, out);
+ if (cbc) {
+ octeon_aes_store_block(crypto->aes_iv, next_iv);
+ }
+}
+
+void helper_octeon_cp2_mt_aes_enc_cbc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_aes_encrypt_common(crypto, true);
+}
+
+void helper_octeon_cp2_mt_aes_enc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_aes_encrypt_common(crypto, false);
+}
+
+void helper_octeon_cp2_mt_aes_dec_cbc1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_aes_decrypt_common(crypto, true);
+}
+
+void helper_octeon_cp2_mt_aes_dec1(CPUMIPSState *env, uint64_t value)
+{
+ MIPSOcteonCryptoState *crypto = &env->octeon_crypto;
+
+ crypto->aes_resinp[1] = value;
+ octeon_aes_decrypt_common(crypto, false);
+}
+
void helper_octeon_cp2_mt_snow3g_start(CPUMIPSState *env, uint64_t value)
{
octeon_snow3g_start(&env->octeon_crypto, value);
--
2.53.0
next prev parent reply other threads:[~2026-07-07 18:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 18:15 [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 01/23] target/mips: add Octeon COP2 crypto state Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 02/23] target/mips: add Octeon COP2 crypto helper plumbing Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 03/23] target/mips: add Octeon CRC COP2 helpers Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 04/23] target/mips: add Octeon GFM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 05/23] target/mips: add Octeon SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 06/23] target/mips: add Octeon ZUC " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 07/23] target/mips: add Octeon SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` Philippe Mathieu-Daudé [this message]
2026-07-07 18:15 ` [PULL 09/23] target/mips: add Octeon SMS4 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 10/23] target/mips: add Octeon 3DES and KASUMI " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 11/23] target/mips: add Octeon Camellia " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 12/23] target/mips: add Octeon HSH " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 13/23] target/mips: add Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 14/23] target/mips: decode Octeon COP2 register selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 15/23] target/mips: decode Octeon CRC and GFM COP2 selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 16/23] target/mips: decode Octeon HSH and SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 17/23] target/mips: decode Octeon ZUC and SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 18/23] target/mips: decode Octeon block-cipher " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 19/23] target/mips: decode Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 20/23] target/mips: add Octeon CvmCount RDHWR support Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 21/23] tests/tcg/mips: cover Octeon QMAC instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 22/23] target/sh4: fixup tcg for sh4 fipr/ftrv instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 23/23] qemu-options: Do not list -enable-kvm on MIPS binaries Philippe Mathieu-Daudé
2026-07-08 5:19 ` [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-08 15:32 ` Stefan Hajnoczi
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