From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Subject: [PULL 01/23] target/mips: add Octeon COP2 crypto state
Date: Tue, 7 Jul 2026 20:15:06 +0200 [thread overview]
Message-ID: <20260707181529.60191-2-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260707181529.60191-1-philmd@oss.qualcomm.com>
From: James Hilliard <james.hilliard1@gmail.com>
Add the common architectural state needed by Octeon's selector-driven
COP2 crypto interfaces. This includes storage for the base hash, AES,
CRC, GFM, 3DES, KASUMI, and overlapping HSH/SHA512/SHA3/SNOW3G/ZUC
selector windows.
Keep selector values and helper-local aliasing logic out of the CPU state
header so the state definition remains limited to architectural storage.
Helper code uses the same register banks instead of adding
non-architectural shadow state. Model the SHA3 view as a direct 25-lane
alias of the architectural HSH DAT/IV/SHA3_DAT24 storage.
Migrate the state in an Octeon-only subsection so non-Octeon CPU models
do not grow migration data.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260608-mips-octeon-missing-insns-v2-v16-1-daef7a0d8b04@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/mips/cpu.h | 26 ++++++++++++++++++++++++++
target/mips/system/machine.c | 27 +++++++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 392406aff8a..3df71adf9bd 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -537,6 +537,30 @@ struct TCState {
};
struct MIPSITUState;
+typedef struct MIPSOcteonCryptoState {
+ union {
+ struct {
+ uint64_t hsh_dat[16];
+ uint64_t hsh_iv[8];
+ uint64_t sha3_dat24;
+ };
+ uint64_t sha3_dat[25];
+ };
+ uint64_t des3_key[3];
+ uint64_t des3_iv;
+ uint64_t des3_result;
+ uint64_t aes_resinp[2];
+ uint64_t aes_iv[2];
+ uint64_t aes_key[4];
+ uint32_t crc_poly;
+ uint32_t crc_iv;
+ uint64_t gfm_mul[2];
+ uint64_t gfm_resinp[2];
+ uint16_t gfm_poly;
+ uint8_t aes_keylen;
+ uint8_t crc_len;
+} MIPSOcteonCryptoState;
+
typedef struct CPUArchState {
TCState active_tc;
CPUMIPSFPUContext active_fpu;
@@ -558,6 +582,8 @@ typedef struct CPUArchState {
#define MSAIR_ProcID 8
#define MSAIR_Rev 0
+ MIPSOcteonCryptoState octeon_crypto;
+
/*
* CP0 Register 0
*/
diff --git a/target/mips/system/machine.c b/target/mips/system/machine.c
index f988b3695bc..77f576a25b1 100644
--- a/target/mips/system/machine.c
+++ b/target/mips/system/machine.c
@@ -279,6 +279,32 @@ static const VMStateDescription mips_vmstate_octeon_multiplier = {
}
};
+static const VMStateDescription mips_vmstate_octeon_crypto = {
+ .name = "cpu/octeon_crypto",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = mips_octeon_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_dat, MIPSCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.hsh_iv, MIPSCPU, 8),
+ VMSTATE_UINT64(env.octeon_crypto.sha3_dat24, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.des3_key, MIPSCPU, 3),
+ VMSTATE_UINT64(env.octeon_crypto.des3_iv, MIPSCPU),
+ VMSTATE_UINT64(env.octeon_crypto.des3_result, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_resinp, MIPSCPU, 2),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_iv, MIPSCPU, 2),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.aes_key, MIPSCPU, 4),
+ VMSTATE_UINT32(env.octeon_crypto.crc_poly, MIPSCPU),
+ VMSTATE_UINT32(env.octeon_crypto.crc_iv, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_mul, MIPSCPU, 2),
+ VMSTATE_UINT64_ARRAY(env.octeon_crypto.gfm_resinp, MIPSCPU, 2),
+ VMSTATE_UINT16(env.octeon_crypto.gfm_poly, MIPSCPU),
+ VMSTATE_UINT8(env.octeon_crypto.aes_keylen, MIPSCPU),
+ VMSTATE_UINT8(env.octeon_crypto.crc_len, MIPSCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
.version_id = 21,
@@ -396,6 +422,7 @@ const VMStateDescription vmstate_mips_cpu = {
.subsections = (const VMStateDescription * const []) {
&mips_vmstate_timer,
&mips_vmstate_octeon_multiplier,
+ &mips_vmstate_octeon_crypto,
NULL
}
};
--
2.53.0
next prev parent reply other threads:[~2026-07-07 18:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-07 18:15 [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-07 18:15 ` Philippe Mathieu-Daudé [this message]
2026-07-07 18:15 ` [PULL 02/23] target/mips: add Octeon COP2 crypto helper plumbing Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 03/23] target/mips: add Octeon CRC COP2 helpers Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 04/23] target/mips: add Octeon GFM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 05/23] target/mips: add Octeon SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 06/23] target/mips: add Octeon ZUC " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 07/23] target/mips: add Octeon SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 08/23] target/mips: add Octeon AES " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 09/23] target/mips: add Octeon SMS4 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 10/23] target/mips: add Octeon 3DES and KASUMI " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 11/23] target/mips: add Octeon Camellia " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 12/23] target/mips: add Octeon HSH " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 13/23] target/mips: add Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 14/23] target/mips: decode Octeon COP2 register selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 15/23] target/mips: decode Octeon CRC and GFM COP2 selectors Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 16/23] target/mips: decode Octeon HSH and SHA3 " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 17/23] target/mips: decode Octeon ZUC and SNOW3G " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 18/23] target/mips: decode Octeon block-cipher " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 19/23] target/mips: decode Octeon CHORD and LLM " Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 20/23] target/mips: add Octeon CvmCount RDHWR support Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 21/23] tests/tcg/mips: cover Octeon QMAC instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 22/23] target/sh4: fixup tcg for sh4 fipr/ftrv instructions Philippe Mathieu-Daudé
2026-07-07 18:15 ` [PULL 23/23] qemu-options: Do not list -enable-kvm on MIPS binaries Philippe Mathieu-Daudé
2026-07-08 5:19 ` [PULL 00/23] MIPS & SH4 patches for 2026-07-07 Philippe Mathieu-Daudé
2026-07-08 15:32 ` Stefan Hajnoczi
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