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From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: Frank.Li@kernel.org, linux-pci@vger.kernel.org,
	imx@lists.linux.dev, neil.armstrong@linaro.org,
	linux-amlogic@lists.infradead.org
Subject: Re: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header
Date: Mon, 20 Jul 2026 15:17:32 +0000	[thread overview]
Message-ID: <20260720151732.7B9A41F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260720150619.24733-2-18255117159@163.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Data race and logically flawed caching in dw_pcie_get_pcie_cap() due to unprotected read-modify-write and failure to cache 'not found' state.
--

--- Patch [1]: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header ---
commit ab22dc6f534d77b34df13c99dd929771547f5ff1
Author: Hans Zhang <18255117159@163.com>

PCI: dwc: Add pcie_cap field and helper in designware header

This commit adds a pcie_cap field to struct dw_pcie to cache the offset of
the PCI Express Capability structure. It introduces dw_pcie_get_pcie_cap()
to perform the capability search on the first call and cache the result.

> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
[ ... ]
> @@ -829,6 +831,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
>  	dw_pcie_writel_dbi(pci, reg, val);
>  }
>  
> +/**
> + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset
> + * @pci: DWC instance
> + *
> + * Finds and caches the offset of PCI_CAP_ID_EXP on first call.
> + * Returns 0 if the capability is not present.
> + */
> +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci)
> +{
> +	if (!pci->pcie_cap)
> +		pci->pcie_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

[Severity: Medium]
Will this repeatedly search the configuration space if the capability is
not found? If dw_pcie_find_capability() returns 0 when the capability is
missing, pci->pcie_cap will remain 0, causing the search to be repeated
on every subsequent call instead of being cached.

Also, since this helper might be called concurrently by different threads,
could the unprotected read and write to pci->pcie_cap cause a data race?

> +
> +	return pci->pcie_cap;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720150619.24733-1-18255117159@163.com?part=1

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WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Hans Zhang" <18255117159@163.com>
Cc: Frank.Li@kernel.org, linux-pci@vger.kernel.org,
	imx@lists.linux.dev, neil.armstrong@linaro.org,
	linux-amlogic@lists.infradead.org
Subject: Re: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header
Date: Mon, 20 Jul 2026 15:17:32 +0000	[thread overview]
Message-ID: <20260720151732.7B9A41F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260720150619.24733-2-18255117159@163.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Data race and logically flawed caching in dw_pcie_get_pcie_cap() due to unprotected read-modify-write and failure to cache 'not found' state.
--

--- Patch [1]: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header ---
commit ab22dc6f534d77b34df13c99dd929771547f5ff1
Author: Hans Zhang <18255117159@163.com>

PCI: dwc: Add pcie_cap field and helper in designware header

This commit adds a pcie_cap field to struct dw_pcie to cache the offset of
the PCI Express Capability structure. It introduces dw_pcie_get_pcie_cap()
to perform the capability search on the first call and cache the result.

> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
[ ... ]
> @@ -829,6 +831,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
>  	dw_pcie_writel_dbi(pci, reg, val);
>  }
>  
> +/**
> + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset
> + * @pci: DWC instance
> + *
> + * Finds and caches the offset of PCI_CAP_ID_EXP on first call.
> + * Returns 0 if the capability is not present.
> + */
> +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci)
> +{
> +	if (!pci->pcie_cap)
> +		pci->pcie_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

[Severity: Medium]
Will this repeatedly search the configuration space if the capability is
not found? If dw_pcie_find_capability() returns 0 when the capability is
missing, pci->pcie_cap will remain 0, causing the search to be repeated
on every subsequent call instead of being cached.

Also, since this helper might be called concurrently by different threads,
could the unprotected read and write to pci->pcie_cap cause a data race?

> +
> +	return pci->pcie_cap;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260720150619.24733-1-18255117159@163.com?part=1

  reply	other threads:[~2026-07-20 15:17 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-20 15:06 [PATCH v3 00/16] PCI: dwc: Cache PCIe capability offset and simplify drivers Hans Zhang
2026-07-20 15:06 ` Hans Zhang
2026-07-20 15:06 ` Hans Zhang
2026-07-20 15:06 ` Hans Zhang
2026-07-20 15:06 ` [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:17   ` sashiko-bot [this message]
2026-07-20 15:17     ` sashiko-bot
2026-07-20 15:27     ` Hans Zhang
2026-07-20 15:27       ` Hans Zhang
2026-07-20 15:06 ` [PATCH v3 02/16] PCI: dwc: Use cached PCIe capability offset in core Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:28   ` sashiko-bot
2026-07-20 15:28     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:28   ` sashiko-bot
2026-07-20 15:28     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 04/16] PCI: dwc: layerscape-ep: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:25   ` sashiko-bot
2026-07-20 15:25     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 05/16] PCI: dwc: meson: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:17   ` sashiko-bot
2026-07-20 15:17     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 06/16] PCI: dwc: rockchip: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:21   ` sashiko-bot
2026-07-20 15:21     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 07/16] PCI: dwc: eswin: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:15   ` sashiko-bot
2026-07-20 15:15     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 08/16] PCI: dwc: fu740: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:26   ` sashiko-bot
2026-07-20 15:26     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 09/16] PCI: dwc: intel-gw: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:23   ` sashiko-bot
2026-07-20 15:23     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 10/16] PCI: dwc: qcom-ep: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:29   ` sashiko-bot
2026-07-20 15:29     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 11/16] PCI: dwc: qcom: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:19   ` sashiko-bot
2026-07-20 15:19     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 12/16] PCI: dwc: sophgo: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:20   ` sashiko-bot
2026-07-20 15:20     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 13/16] PCI: dwc: spacemit-k1: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:19   ` sashiko-bot
2026-07-20 15:19     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 14/16] PCI: dwc: spear13xx: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:27   ` sashiko-bot
2026-07-20 15:27     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 15/16] PCI: dwc: tegra194: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:30   ` sashiko-bot
2026-07-20 15:30     ` sashiko-bot
2026-07-20 15:06 ` [PATCH v3 16/16] PCI: dwc: ultrarisc: " Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:06   ` Hans Zhang
2026-07-20 15:33   ` sashiko-bot
2026-07-20 15:33     ` sashiko-bot

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