From: Joel Stanley <joel@jms.id.au>
To: "Alistair Francis" <alistair.francis@wdc.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Nicholas Piggin <npiggin@gmail.com>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Michael Ellerman <mpe@kernel.org>,
Portia Stephens <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: [PATCH 10/12] tests/tcg/riscv64: Enable vectorised memory test
Date: Thu, 27 Aug 2026 14:39:49 +0930 [thread overview]
Message-ID: <20260827050953.67184-11-joel@jms.id.au> (raw)
In-Reply-To: <20260827050953.67184-1-joel@jms.id.au>
Build memory.c a second time with -march=rv64gcv -O3, similar to
aarch64's memory-sve, so the memory test checks RVV loads and
stores, including across page boundaries.
Run it under -cpu rv64,v=true.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 3f2a8ed16142..301a6e6e5700 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -76,6 +76,14 @@ EXTRA_RUNS += $(MULTIARCH_RUNS)
# Default is zicclsm=true, so misaligned accesses must work
memory: private CFLAGS += -DCHECK_UNALIGNED=1
+memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(call quiet-command, \
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@)
+memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
+run-memory-rvv: QEMU_CPU = rv64,v=true
+
+TESTS += memory-rvv
+
# Simple Record/Replay Test
.PHONY: memory-record
run-memory-record: memory-record memory
--
2.47.3
next prev parent reply other threads:[~2026-08-27 5:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
2026-08-31 1:07 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
2026-08-31 1:09 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
2026-08-31 1:10 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
2026-08-31 1:14 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
2026-08-31 1:17 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
2026-08-31 1:20 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
2026-08-31 1:21 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
2026-08-27 5:09 ` Joel Stanley [this message]
2026-08-31 1:25 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Alistair Francis
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
2026-08-31 1:26 ` Alistair Francis
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
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