From: Joel Stanley <joel@jms.id.au>
To: "Alistair Francis" <alistair.francis@wdc.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Nicholas Piggin <npiggin@gmail.com>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Michael Ellerman <mpe@kernel.org>,
Portia Stephens <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops
Date: Thu, 27 Aug 2026 14:39:51 +0930 [thread overview]
Message-ID: <20260827050953.67184-13-joel@jms.id.au> (raw)
In-Reply-To: <20260827050953.67184-1-joel@jms.id.au>
Disassemble the tests and count the SVE or RVV memory access. Delete the
binary when the check fails otherwise a subsequent run will not run the
check and silently succeed.
CHECK memory-rvv contains 7 vector loads and 7 stores
CHECK memory-sve contains 20 vector loads and 17 stores
This is a coarse check and could be improved by checking specific
functions, and using something more precise than an opcode grep.
However, it would have caught the bug fixed in "tests/tcg/multiarch: Fix
vectorisation of memory test", which makes it worthwhile.
Skipped when no cross objdump was found.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/Makefile.target | 8 ++++++++
tests/tcg/aarch64/Makefile.softmmu-target | 1 +
tests/tcg/riscv64/Makefile.softmmu-target | 1 +
3 files changed, 10 insertions(+)
diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index d4dd0fec650d..a5b694d2f21c 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -79,6 +79,14 @@ conditional-diff-out = \
$(call diff-out,$1,$2), \
$(call skip-test,"$1 check","no reference"))
+# Check an ELF for vector load ($1) and store ($2) patterns.
+# Deleted on failure so the check runs again on the next make.
+check-vectorised = $(if $(OBJDUMP), \
+ $(call quiet-command, \
+ ld=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$1'); \
+ st=$$($(OBJDUMP) -d $@ | grep -cE '[[:space:]]$2'); \
+ printf " %-7s %s\n" CHECK "$@ contains $$ld vector loads and $$st stores"; \
+ test "$$ld" -gt 0 && test "$$st" -gt 0 || { rm -f $@; exit 1; }))
# Tests we are building
TESTS=
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
index 196a2afa50ee..99ad1a2799d7 100644
--- a/tests/tcg/aarch64/Makefile.softmmu-target
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
@@ -50,6 +50,7 @@ memory: CFLAGS+=-DCHECK_UNALIGNED=1
memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) boot.o
+ $(call check-vectorised,ld1[bhwds],st1[bhwd])
memory-sve: private CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 301a6e6e5700..5262007e39a5 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -79,6 +79,7 @@ memory: private CFLAGS += -DCHECK_UNALIGNED=1
memory-rvv: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(call quiet-command, \
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(CRT_OBJS), CC, $@)
+ $(call check-vectorised,vle,vse[0-9])
memory-rvv: private CFLAGS += -DCHECK_UNALIGNED=1 -march=rv64gcv -O3
run-memory-rvv: QEMU_CPU = rv64,v=true
--
2.47.3
next prev parent reply other threads:[~2026-08-27 5:13 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
2026-08-31 1:07 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
2026-08-31 1:09 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Joel Stanley
2026-08-31 1:10 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
2026-08-31 1:14 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
2026-08-31 1:17 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
2026-08-31 1:20 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
2026-08-31 1:21 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` Joel Stanley [this message]
2026-08-31 1:26 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Alistair Francis
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
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