From: Joel Stanley <joel@jms.id.au>
To: "Alistair Francis" <alistair.francis@wdc.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Chao Liu <chao.liu@processmission.com>,
Nicholas Piggin <npiggin@gmail.com>,
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Michael Ellerman <mpe@kernel.org>,
Portia Stephens <portias@oss.tenstorrent.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
qemu-arm@nongnu.org
Subject: [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel
Date: Thu, 27 Aug 2026 14:39:42 +0930 [thread overview]
Message-ID: <20260827050953.67184-4-joel@jms.id.au> (raw)
In-Reply-To: <20260827050953.67184-1-joel@jms.id.au>
Loading tests should conflict with the opensbi ROM, however the generic
loader writes through the CPU address space which bypasses the ROM
overlap check.
Instead of depending on this happy accident, set -bios none to skip
loading opensbi. This frees up the address space to load the test with
-kernel, required by a future change that uses the same rules to run the
multiarch tests for riscv64.
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
tests/tcg/riscv64/Makefile.softmmu-target | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target
index 6a219c306c43..562ac9b0e0fb 100644
--- a/tests/tcg/riscv64/Makefile.softmmu-target
+++ b/tests/tcg/riscv64/Makefile.softmmu-target
@@ -14,36 +14,36 @@ CFLAGS += -g -Og
%: %.o $(LINK_SCRIPT)
$(LD) $(LDFLAGS) $< -o $@
-QEMU_OPTS += -M virt -display none -semihosting -device loader,file=
+QEMU_OPTS += -M virt -display none -bios none -semihosting -kernel
EXTRA_RUNS += run-issue1060
run-issue1060: issue1060
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-mepc-masking
run-test-mepc-masking: test-mepc-masking
- $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-minstret-ecall
run-test-minstret-ecall: test-minstret-ecall
- $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -icount shift=1 $(QEMU_OPTS) $<)
EXTRA_RUNS += run-plugin-doubletrap
run-plugin-doubletrap: doubletrap
$(call run-test, $<, \
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS)$<)
+ $(QEMU_OPTS) $<)
EXTRA_RUNS += run-plugin-interruptedmemory
run-plugin-interruptedmemory: interruptedmemory
$(call run-test, $<, \
$(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \
- $(QEMU_OPTS)$<)
+ $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-crc32
comma:= ,
run-test-crc32: test-crc32
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS) $<)
# Zicclsm: misaligned load/store support. Assemble one source twice: the
# default build expects every misaligned access to succeed (zicclsm=true),
@@ -61,11 +61,11 @@ test-zicclsm-off: test-zicclsm.S $(LINK_SCRIPT)
EXTRA_RUNS += run-test-zicclsm
run-test-zicclsm: test-zicclsm
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=true $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-zicclsm-off
run-test-zicclsm-off: test-zicclsm-off
- $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS)$<)
+ $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)zfh=true$(comma)zicclsm=false $(QEMU_OPTS) $<)
EXTRA_RUNS += run-test-misa-w
run-test-misa-w: test-misa-w
--
2.47.3
next prev parent reply other threads:[~2026-08-27 5:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 5:09 [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Joel Stanley
2026-08-27 5:09 ` [PATCH 01/12] tests/tcg/riscv64: Include stdint.h in semicall.h Joel Stanley
2026-08-31 1:07 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 02/12] tests/tcg/riscv64: Clean up semicall.h inline asm Joel Stanley
2026-08-31 1:09 ` Alistair Francis
2026-08-27 5:09 ` Joel Stanley [this message]
2026-08-31 1:10 ` [PATCH 03/12] tests/tcg/riscv64: Boot semihost tests with -bios none -kernel Alistair Francis
2026-08-27 5:09 ` [PATCH 04/12] tests/tcg/riscv64: Update semihosting linker script Joel Stanley
2026-08-31 1:14 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 05/12] tests/tcg/riscv64: Rework rules for semihost tests Joel Stanley
2026-08-31 1:17 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 06/12] tests/tcg/riscv64: Enable multiarch system tests Joel Stanley
2026-08-31 1:20 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 07/12] tests/tcg/riscv64: Enable memory record and replay test Joel Stanley
2026-08-31 1:21 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 08/12] tests/tcg/aarch64: Don't leak memory-sve CFLAGS Joel Stanley
2026-09-22 5:39 ` Alistair Francis
2026-09-22 7:17 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 09/12] tests/tcg/multiarch: Fix vectorisation of memory test Joel Stanley
2026-08-31 1:24 ` Alistair Francis
2026-09-01 10:06 ` Alex Bennée
2026-08-27 5:09 ` [PATCH 10/12] tests/tcg/riscv64: Enable vectorised " Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 11/12] configure: Provide OBJDUMP to the tcg tests Joel Stanley
2026-08-31 1:25 ` Alistair Francis
2026-08-27 5:09 ` [PATCH 12/12] tests/tcg: Check vector memory tests contain vector ops Joel Stanley
2026-08-31 1:26 ` Alistair Francis
2026-09-22 9:50 ` [PATCH 00/12] tests/tcg: Multiarch tests for riscv64 Alistair Francis
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