From: sashiko-bot@kernel.org
To: "Dave Jiang" <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org
Subject: Re: [PATCH v5 09/13] ACPI: APEI: GHES: Validate CXL protocol error section length before RAS cap copy
Date: Thu, 27 Aug 2026 20:53:19 +0000 [thread overview]
Message-ID: <20260827205320.5974D1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260827203726.3027541-10-dave.jiang@intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Potential deadlock because `cxl_cper_prot_err_work_lock` is acquired in process context without disabling hardware interrupts.
--
commit 1416c4f9e4b0f4dc84b6e812f70c5f34a5255acc
Author: Dave Jiang <dave.jiang@intel.com>
ACPI: APEI: GHES: Validate CXL protocol error section length before RAS cap copy
cxl_cper_setup_prot_err_work_data() locates the RAS Capability block using an
unvalidated firmware-controlled length, which can point the copy outside the
section. This commit extends cxl_cper_sec_prot_err_valid() to check that the
section can hold the header, DVSEC, and RAS Capability block within the reported
section length.
Link: https://sashiko.dev/#/patchset/20260617-topics-ahmtib01-ras_ffh_arm_internal_review-v6-0-91f725174aa0@arm.com?part=6
Link: https://lore.kernel.org/linux-cxl/20260709165457.8BA181F000E9@smtp.kernel.org/
[ ... ]
> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
> index e5f8dbd17017e..b8dbd99da47ef 100644
> --- a/drivers/acpi/apei/ghes.c
> +++ b/drivers/acpi/apei/ghes.c
> @@ -753,12 +753,12 @@ static DEFINE_SPINLOCK(cxl_cper_prot_err_work_lock);
> struct work_struct *cxl_cper_prot_err_work;
>
> void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err,
> - int severity)
> + int severity, u32 len)
> {
> #ifdef CONFIG_ACPI_APEI_PCIEAER
> struct cxl_cper_prot_err_work_data wd;
>
> - if (cxl_cper_sec_prot_err_valid(prot_err))
> + if (cxl_cper_sec_prot_err_valid(prot_err, len))
> return;
>
> guard(spinlock_irqsave)(&cxl_cper_prot_err_work_lock);
[Severity: High]
This isn't a bug introduced by this patch, but does acquiring this lock in
hardirq context cause a potential deadlock?
If the module initialization thread executes cxl_cper_register_prot_err_work()
(or unregister) in process context, it acquires cxl_cper_prot_err_work_lock
with interrupts enabled:
drivers/acpi/apei/ghes.c:cxl_cper_register_prot_err_work() {
...
guard(spinlock)(&cxl_cper_prot_err_work_lock);
...
}
If a GHES hardware error interrupt fires on the same CPU, executing
ghes_do_proc() -> cxl_cper_post_prot_err(), it will attempt to acquire the
same lock here using guard(spinlock_irqsave).
Would it spin forever waiting for the interrupted process context to release
the lock?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260827203726.3027541-1-dave.jiang@intel.com?part=9
next prev parent reply other threads:[~2026-08-27 20:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 20:37 [PATCH v5 00/13] ACPI: APEI: GHES: Collection of fixes for issues reported by sashiko Dave Jiang
2026-08-27 20:37 ` [PATCH v5 01/13] efi/cper: Reject CPER records with an out-of-range error_data_length Dave Jiang
2026-08-27 20:52 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 02/13] efi/cper: Reject an error status block length that wraps a u32 Dave Jiang
2026-08-27 20:52 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 03/13] ACPI: extlog: Validate elog record length before walking sections Dave Jiang
2026-08-27 20:55 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 04/13] ACPI: extlog: Defer CXL protocol error handling to avoid lock inversion Dave Jiang
2026-08-27 20:55 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 05/13] ACPI: extlog: Avoid populating software AER metadata from raw hardware buffer Dave Jiang
2026-08-27 20:58 ` sashiko-bot
2026-08-27 23:06 ` Dave Jiang
2026-08-27 20:37 ` [PATCH v5 06/13] ACPI: extlog: Validate PCIe error section length before payload access Dave Jiang
2026-08-27 20:37 ` [PATCH v5 07/13] ACPI: extlog: Fix CONFIG_ACPI_APEI_PCIEAER guard typo Dave Jiang
2026-08-27 20:37 ` [PATCH v5 08/13] ACPI: APEI: GHES: Bound CXL event record copy to the firmware section length Dave Jiang
2026-08-27 20:55 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 09/13] ACPI: APEI: GHES: Validate CXL protocol error section length before RAS cap copy Dave Jiang
2026-08-27 20:53 ` sashiko-bot [this message]
2026-08-27 20:37 ` [PATCH v5 10/13] efi/cper: Read only validated fields in cper_mem_err_pack() Dave Jiang
2026-08-27 20:55 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 11/13] ACPI: APEI: GHES: Validate memory error section length before payload access Dave Jiang
2026-08-27 21:05 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 12/13] ACPI: APEI: GHES: Bound AER info copy and sanitize software metadata Dave Jiang
2026-08-27 21:01 ` sashiko-bot
2026-08-27 20:37 ` [PATCH v5 13/13] cxl/ras: Make cxl_cper_handle_prot_err() static Dave Jiang
2026-08-27 20:59 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260827205320.5974D1F000E9@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=dave.jiang@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.