From: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
chao.liu@processmission.com,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>
Subject: [PATCH v5 04/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_riscv_iommu_sys()
Date: Fri, 28 Aug 2026 17:39:06 -0300 [thread overview]
Message-ID: <20260828203918.350131-5-daniel.barboza@oss.qualcomm.com> (raw)
In-Reply-To: <20260828203918.350131-1-daniel.barboza@oss.qualcomm.com>
Both the 'virt' board and the future 'riscv-server-ref' boards uses an
iommu-sys device that is declared in the DT. Create a helper to
encapsulate the logic and avoid copy/pasting stuff between boards.
The helper will return the iommu phandle value instead of returning void
and writing the used phandle in an extra argument.
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
---
hw/riscv/fdt-common.c | 35 ++++++++++++++++++++++++
hw/riscv/virt.c | 50 ++++++-----------------------------
include/hw/riscv/fdt-common.h | 5 ++++
3 files changed, 48 insertions(+), 42 deletions(-)
diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c
index eac5ca9322..88589330fb 100644
--- a/hw/riscv/fdt-common.c
+++ b/hw/riscv/fdt-common.c
@@ -13,6 +13,8 @@
#include "hw/core/boards.h"
#include "hw/riscv/fdt-common.h"
#include "target/riscv/cpu_bits.h"
+#include "hw/riscv/riscv-iommu-bits.h"
+#include "hw/riscv/iommu.h"
void *riscv_create_board_device_tree(const char *model, const char *compatible,
int *fdt_size)
@@ -349,3 +351,36 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle,
qemu_fdt_setprop_cell(fdt, name, "value", poweroff);
g_free(name);
}
+
+uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size,
+ uint32_t *next_phandle,
+ uint32_t irq_chip,
+ uint32_t msi_phandle,
+ uint32_t iommu_sys_irq)
+{
+ const char comp[] = "riscv,iommu";
+ g_autofree char *iommu_node = NULL;
+ uint32_t iommu_phandle;
+
+ iommu_node = g_strdup_printf("/soc/iommu@%"HWADDR_PRIx, addr);
+ qemu_fdt_add_subnode(fdt, iommu_node);
+
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
+
+ iommu_phandle = next_phandle ? (*next_phandle)++ : qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
+
+ qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
+
+ qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
+ iommu_sys_irq + RISCV_IOMMU_INTR_CQ, FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_sys_irq + RISCV_IOMMU_INTR_FQ, FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_sys_irq + RISCV_IOMMU_INTR_PM, FDT_IRQ_TYPE_EDGE_LOW,
+ iommu_sys_irq + RISCV_IOMMU_INTR_PQ, FDT_IRQ_TYPE_EDGE_LOW);
+
+ qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
+
+ return iommu_phandle;
+}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ab6c53c78a..8a165f4d9e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -869,46 +869,6 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
}
-static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
- uint32_t msi_phandle,
- uint32_t *iommu_sys_phandle)
-{
- const char comp[] = "riscv,iommu";
- void *fdt = MACHINE(s)->fdt;
- uint32_t iommu_phandle;
- g_autofree char *iommu_node = NULL;
- hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base;
- hwaddr size = s->memmap[VIRT_IOMMU_SYS].size;
- uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {
- IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
- IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
- IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
- IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
- };
-
- iommu_node = g_strdup_printf("/soc/iommu@%x",
- (unsigned int) s->memmap[VIRT_IOMMU_SYS].base);
- iommu_phandle = qemu_fdt_alloc_phandle(fdt);
- qemu_fdt_add_subnode(fdt, iommu_node);
-
- qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
- qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
- qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
-
- qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
- qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
-
- qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
- iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
- iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
- iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
- iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
-
- qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
-
- *iommu_sys_phandle = iommu_phandle;
-}
-
static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
{
const char comp[] = "riscv,pci-iommu";
@@ -947,8 +907,14 @@ static void finalize_fdt(RISCVVirtState *s)
create_fdt_virtio(s, irq_virtio_phandle);
if (virt_is_iommu_sys_enabled(s)) {
- create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
- &iommu_sys_phandle);
+ iommu_sys_phandle =
+ riscv_create_fdt_riscv_iommu_sys(MACHINE(s)->fdt,
+ s->memmap[VIRT_IOMMU_SYS].base,
+ s->memmap[VIRT_IOMMU_SYS].size,
+ &phandle,
+ irq_mmio_phandle,
+ msi_pcie_phandle,
+ IOMMU_SYS_IRQ);
}
create_fdt_pcie(s, irq_pcie_phandle, msi_pcie_phandle,
iommu_sys_phandle);
diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h
index e377682b32..65711468b8 100644
--- a/include/hw/riscv/fdt-common.h
+++ b/include/hw/riscv/fdt-common.h
@@ -43,4 +43,9 @@ void riscv_create_fdt_syscon(void *fdt, uint32_t *next_phandle,
hwaddr addr, hwaddr size,
uint32_t reboot, uint32_t poweroff,
bool sifive_test_compat);
+uint32_t riscv_create_fdt_riscv_iommu_sys(void *fdt, hwaddr addr, hwaddr size,
+ uint32_t *next_phandle,
+ uint32_t irq_chip,
+ uint32_t msi_phandle,
+ uint32_t iommu_sys_irq);
#endif
--
2.43.0
next prev parent reply other threads:[~2026-08-28 20:41 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-28 20:39 [PATCH v5 00/15] hw/riscv: trivial code dup work (riscv-server-ref prep) Daniel Henrique Barboza
2026-08-28 20:39 ` [PATCH v5 01/15] hw/riscv/fdt-common: prepend helpers with "riscv_" Daniel Henrique Barboza
2026-09-01 4:42 ` Alistair Francis
2026-09-02 16:24 ` Philippe Mathieu-Daudé
2026-09-02 16:38 ` Daniel Henrique Barboza
2026-08-28 20:39 ` [PATCH v5 02/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_flash() Daniel Henrique Barboza
2026-09-01 4:45 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 03/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_syscon() Daniel Henrique Barboza
2026-09-01 4:45 ` Alistair Francis
2026-08-28 20:39 ` Daniel Henrique Barboza [this message]
2026-09-01 4:47 ` [PATCH v5 04/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_riscv_iommu_sys() Alistair Francis
2026-08-28 20:39 ` [PATCH v5 05/15] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_pcie() Daniel Henrique Barboza
2026-08-29 3:08 ` Chao Liu via
2026-08-29 3:08 ` Chao Liu via qemu development
2026-09-01 4:49 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 06/15] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_imsic() Daniel Henrique Barboza
2026-08-29 3:08 ` Chao Liu via
2026-08-29 3:08 ` Chao Liu via qemu development
2026-09-01 4:51 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 07/15] hw/riscv/fdt_common, virt.c: add riscv_create_fdt_socket_aplic() Daniel Henrique Barboza
2026-08-29 3:09 ` Chao Liu via
2026-08-29 3:09 ` Chao Liu via qemu development
2026-09-01 5:14 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 08/15] hw/riscv/virt.c: fix aclint soc/mtimer nodename Daniel Henrique Barboza
2026-08-29 3:10 ` Chao Liu
2026-09-01 5:15 ` Alistair Francis
2026-09-16 6:35 ` Michael Tokarev
2026-09-16 17:10 ` Daniel Henrique Barboza
2026-09-17 5:58 ` Chao Liu via qemu development
2026-09-17 5:58 ` Chao Liu via
2026-09-17 12:56 ` Daniel Henrique Barboza
2026-09-17 8:19 ` Michael Tokarev
2026-08-28 20:39 ` [PATCH v5 09/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_socket_aclint() Daniel Henrique Barboza
2026-08-29 3:10 ` Chao Liu via
2026-08-29 3:10 ` Chao Liu via qemu development
2026-09-01 5:17 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 10/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_uart() Daniel Henrique Barboza
2026-08-29 3:11 ` Chao Liu via qemu development
2026-08-29 3:11 ` Chao Liu via
2026-09-01 5:23 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 11/15] hw/riscv/fdt-common, virt.c: add riscv_create_fdt_rtc() Daniel Henrique Barboza
2026-08-29 3:12 ` Chao Liu via qemu development
2026-08-29 3:12 ` Chao Liu via
2026-09-01 5:23 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 12/15] hw/riscv/device-common, virt.c: add riscv_create_platform_bus() Daniel Henrique Barboza
2026-08-29 3:12 ` Chao Liu via
2026-08-29 3:12 ` Chao Liu via qemu development
2026-09-01 5:24 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 13/15] hw/riscv/device-common, virt.c: add flash helpers Daniel Henrique Barboza
2026-08-29 3:12 ` Chao Liu via qemu development
2026-08-29 3:12 ` Chao Liu via
2026-09-01 5:28 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 14/15] hw/riscv/device-common, virt.c: add riscv_gpex_pcie_init() Daniel Henrique Barboza
2026-08-29 3:13 ` Chao Liu via
2026-08-29 3:13 ` Chao Liu via qemu development
2026-09-01 5:28 ` Alistair Francis
2026-08-28 20:39 ` [PATCH v5 15/15] hw/riscv/riscv-iommu-sys.c, virt.c: add riscv_create_iommu_sys() Daniel Henrique Barboza
2026-08-29 3:13 ` Chao Liu via qemu development
2026-08-29 3:13 ` Chao Liu via
2026-09-01 5:28 ` Alistair Francis
2026-09-01 5:32 ` [PATCH v5 00/15] hw/riscv: trivial code dup work (riscv-server-ref prep) Alistair Francis
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