Re: [PATCH v5 15/15] hw/riscv/riscv-iommu-sys.c, virt.c: add riscv_create_iommu_sys()

[Chao Liu via qemu development <qemu-devel@nongnu.org>]

On Fri, Aug 28, 2026 at 05:39:17PM +0800, Daniel Henrique Barboza wrote:
> Move the creation of riscv-iommu-sys to its own file instead of open
> coding it in the 'virt' board.  Other boards in the future might want to
> use this device and we want to avoid code duplication.
> 
> Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao

> ---
>  hw/riscv/riscv-iommu-sys.c | 25 +++++++++++++++++++++++++
>  hw/riscv/riscv-iommu.h     |  3 +++
>  hw/riscv/virt.c            | 23 +++--------------------
>  3 files changed, 31 insertions(+), 20 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
> index 3314adeed2..258c171efd 100644
> --- a/hw/riscv/riscv-iommu-sys.c
> +++ b/hw/riscv/riscv-iommu-sys.c
> @@ -217,6 +217,31 @@ static void riscv_iommu_sys_init(Object *obj)
>      riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
>  }
>  
> +DeviceState *riscv_create_iommu_sys(DeviceState *mmio_irqchip,
> +                                    hwaddr addr, int base_irq,
> +                                    bool is_32_bit)
> +{
> +    DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
> +
> +    object_property_set_uint(OBJECT(iommu_sys), "addr", addr, &error_fatal);
> +    object_property_set_uint(OBJECT(iommu_sys), "base-irq",
> +                             base_irq, &error_fatal);
> +    object_property_set_link(OBJECT(iommu_sys), "irqchip",
> +                             OBJECT(mmio_irqchip),
> +                             &error_fatal);
> +    /*
> +     * For riscv64 use a physical address size of 56 bits (44 bit PPN),
> +     * and for riscv32 use 34 bits (22 bit PPN).
> +     */
> +    object_property_set_uint(OBJECT(iommu_sys), "pas-bits",
> +                             is_32_bit ? 34 : 56,
> +                             &error_fatal);
> +
> +    sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
> +
> +    return iommu_sys;
> +}
> +
>  static const Property riscv_iommu_sys_properties[] = {
>      DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
>      DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
> diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
> index da70e8bfa8..7c470ba084 100644
> --- a/hw/riscv/riscv-iommu.h
> +++ b/hw/riscv/riscv-iommu.h
> @@ -104,6 +104,9 @@ void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
>  void riscv_iommu_reset(RISCVIOMMUState *s);
>  void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type);
>  void riscv_iommu_fault(RISCVIOMMUState *s, struct riscv_iommu_fq_record *ev);
> +DeviceState *riscv_create_iommu_sys(DeviceState *mmio_irqchip,
> +                                    hwaddr addr, int base_irq,
> +                                    bool is_32_bit);
>  
>  typedef struct RISCVIOMMUContext RISCVIOMMUContext;
>  /* Device translation context state. */
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index d75dec2dd2..de7b99c6a5 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -32,6 +32,7 @@
>  #include "hw/core/sysbus-fdt.h"
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/riscv/iommu.h"
> +#include "hw/riscv/riscv-iommu.h"
>  #include "hw/riscv/riscv-iommu-bits.h"
>  #include "hw/riscv/virt.h"
>  #include "hw/riscv/boot.h"
> @@ -933,26 +934,8 @@ static void virt_machine_init(MachineState *machine)
>      }
>  
>      if (virt_is_iommu_sys_enabled(s)) {
> -        DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
> -
> -        object_property_set_uint(OBJECT(iommu_sys), "addr",
> -                                 s->memmap[VIRT_IOMMU_SYS].base,
> -                                 &error_fatal);
> -        object_property_set_uint(OBJECT(iommu_sys), "base-irq",
> -                                 IOMMU_SYS_IRQ,
> -                                 &error_fatal);
> -        object_property_set_link(OBJECT(iommu_sys), "irqchip",
> -                                 OBJECT(mmio_irqchip),
> -                                 &error_fatal);
> -        /*
> -         * For riscv64 use a physical address size of 56 bits (44 bit PPN),
> -         * and for riscv32 use 34 bits (22 bit PPN).
> -         */
> -        object_property_set_uint(OBJECT(iommu_sys), "pas-bits",
> -                                 riscv_is_32bit(&s->soc[0]) ? 34 : 56,
> -                                 &error_fatal);
> -
> -        sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
> +        riscv_create_iommu_sys(mmio_irqchip, s->memmap[VIRT_IOMMU_SYS].base,
> +                               IOMMU_SYS_IRQ, riscv_is_32bit(&s->soc[0]));
>      }
>  
>      s->machine_done.notify = virt_machine_done;
> -- 
> 2.43.0
>