[PATCH 0/2] Support multiple DDR configs in PX30 TPL

[PATCH 0/2] Support multiple DDR configs in PX30 TPL

[Massimo Pegorer]

TPL max size for Rockchip PX30 SoC is very low, but 10240 bytes are
enough to store in two DDR configuration parameters sets if option
CONFIG_RAM_ROCKCHIP_DEBUG is deselected.

The approach is trivial: apply supported DDR config sets in a predefined
order (DDR4, LPDDR2, LPDDR3, DDR3) stopping at the first one that makes
SDRAM initialization function to complete with success. If a smarter
cleverer or more reliable approach exists, suggestions are welcome.

The patches have been tested on two boards, one equipped with DDR3 and
the other with DDR4. All possible sets selections have been tested,
even with orders different from predefined one (e.g. DDR3, LPDDR2,
LPDDR3, DDR4). It would be useful if further tests will be run on other
PX30 based boards.

The patches does not affect binary code of TPL for any of the existing
U-Boot configurations.

The first patch improves clarity of DDR type support selection for
Rockchip SoCs at Kconfig level. Not all the DDR type config options
named in the Kconfig are supported by each one of the Rockchip SoCs.
Moreover, the LPDDR4 option has a different meaning in the context of
the RK3399 SoC than in the RV1126 one. Thus, split options with ad-hoc
specific help sections and use depends on conditionals.

The second patch splits RV1126 options (at most one should be selected)
from PX30 options (more options can be selected), and adds DDR3 option
for PX30. The PX30 sdram driver includes all of the selected DDR type
sets or just the DDR3 one if none is selected: not like it too much but
I preferred to preserve default fallback behavior (include DDR3 support
if no option is selected) to avoid modifing boards configs relying on
it. The parameters sets are applied as already described.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
---
Massimo Pegorer (2):
      ram: rockchip: improve ddr type configs selection
      ram: rockchip: px30: allow multiple DDR types selection

 drivers/ram/rockchip/Kconfig      | 78 ++++++++++++++++++++++++++++++++++++---
 drivers/ram/rockchip/sdram_px30.c | 35 +++++++++++-------
 2 files changed, 93 insertions(+), 20 deletions(-)
---
base-commit: 964ad5b5c91b7be56e443e899d7f873e6aa8c9fc
change-id: 20260828-ddr-multi-2c4fd64344c8

Best regards,
--  
Massimo Pegorer <massimo.pegorer+oss@gmail.com>

[PATCH 1/2] ram: rockchip: improve ddr type configs selection

[Massimo Pegorer]

Not all the DDR type config options named in the Kconfig are supported
by each one of the Rockchip SoCs. Moreover, the LPDDR4 option has a
different meaning in the context of the RK3399 SoC than in the RV1126
one. Improve clarity splitting config options, using SoC specific help
sections and adding depends on conditionals.

Involved Rockchip SoCs are: RK3399, PX30, RV1126.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
---
 drivers/ram/rockchip/Kconfig | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index d707d09c1c8..61a3193b3f5 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -26,26 +26,53 @@ config RAM_ROCKCHIP_DEBUG
 
 config RAM_ROCKCHIP_DDR4
 	bool "DDR4 support for Rockchip SoCs"
+	depends on ROCKCHIP_PX30 || ROCKCHIP_RV1126
 	help
 	  This enables DDR4 sdram support instead of the default DDR3 support
 	  on Rockchip SoCs.
 
+	  Note that even if multiple DDR/LPDDR types are selected, support is
+	  enabled only for the selected one that comes first in the following
+	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+
 config RAM_ROCKCHIP_LPDDR2
 	bool "LPDDR2 support for Rockchip SoCs"
+	depends on ROCKCHIP_PX30
 	help
 	  This enables LPDDR2 sdram support instead of the default DDR3 support
 	  on Rockchip SoCs.
 
+	  Note that even if multiple DDR/LPDDR types are selected, support is
+	  enabled only for the selected one that comes first in the following
+	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+
 config RAM_ROCKCHIP_LPDDR3
 	bool "LPDDR3 support for Rockchip SoCs"
+	depends on ROCKCHIP_PX30
 	help
 	  This enables LPDDR3 sdram support instead of the default DDR3 support
 	  on Rockchip SoCs.
 
+	  Note that even if multiple DDR/LPDDR types are selected, support is
+	  enabled only for the selected one that comes first in the following
+	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+
 config RAM_ROCKCHIP_LPDDR4
+	depends on ROCKCHIP_RV1126
 	bool "LPDDR4 support for Rockchip SoCs"
 	help
-	  This enables LPDDR4 sdram code support for the platforms based
+	  This enables LPDDR4 sdram support instead of the default DDR3 support
 	  on Rockchip SoCs.
 
+	  Note that even if multiple DDR/LPDDR types are selected, support is
+	  enabled only for the selected one that comes first in the following
+	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+
+config RAM_ROCKCHIP_LPDDR4
+	bool "LPDDR4 support for Rockchip SoCs"
+	depends on ROCKCHIP_RK3399
+	help
+	  This enables LPDDR4 sdram code support for the platforms based
+	  on Rockchip RK3399 SoC.
+
 endif # RAM_ROCKCHIP

-- 
2.34.1

[PATCH 2/2] ram: rockchip: px30: allow multiple DDR types selection

[Massimo Pegorer]

Allow the inclusion of more than one DDR parameters set in the PX30
SDRAM driver. The driver applies included sets in a predefined order
(DDR4, LPDDR2, LPDDR3, DDR3), stopping at the first one that makes
SDRAM initialization function to complete with success.

The default fallback behaviour is preserved: if no DDR configuration
option is selected, DDR3 parameters set is included.

Due to limited PX30 TPL maximum size, including support for more than
one DDR type requires disabling some configuration options such as
CONFIG_RAM_ROCKCHIP_DEBUG.

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
---
 drivers/ram/rockchip/Kconfig      | 67 +++++++++++++++++++++++++++++++--------
 drivers/ram/rockchip/sdram_px30.c | 35 ++++++++++++--------
 2 files changed, 74 insertions(+), 28 deletions(-)

diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig
index 61a3193b3f5..d74980402ad 100644
--- a/drivers/ram/rockchip/Kconfig
+++ b/drivers/ram/rockchip/Kconfig
@@ -24,38 +24,77 @@ config RAM_ROCKCHIP_DEBUG
 	  This is an option for developers to understand the ram drivers
 	  initialization, configurations and etc.
 
+config RAM_ROCKCHIP_DDR3
+	bool "DDR3 support for Rockchip SoCs"
+	depends on ROCKCHIP_PX30
+	help
+	  Enable DDR3 sdram support on Rockchip SoCs.
+
+	  Note that enabling support for multiple DDR/LPDDR types may cause TPL
+	  to exceed its maximum size constraint (TPL_MAX_SIZE), depending on
+	  other configuration options selection (such as RAM_ROCKCHIP_DEBUG).
+
+	  The driver applies selected sdram parameters sets in the following
+	  order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes
+	  sdram_init_detect() to complete successfully.
+
+	  If no DDR/LPDDR option is selected, DDR3 sdram support is enabled by
+	  default for backward compatibility with existing board configurations.
+	  Therefore this option is only useful for multiple DDR/LPDDR types
+	  selection.
+
 config RAM_ROCKCHIP_DDR4
 	bool "DDR4 support for Rockchip SoCs"
-	depends on ROCKCHIP_PX30 || ROCKCHIP_RV1126
+	depends on ROCKCHIP_PX30
 	help
-	  This enables DDR4 sdram support instead of the default DDR3 support
-	  on Rockchip SoCs.
+	  Enable DDR4 sdram support on Rockchip SoCs.
 
-	  Note that even if multiple DDR/LPDDR types are selected, support is
-	  enabled only for the selected one that comes first in the following
-	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+	  Note that enabling support for multiple DDR/LPDDR types may cause TPL
+	  to exceed its maximum size constraint (TPL_MAX_SIZE), depending on
+	  other configuration options selection (such as RAM_ROCKCHIP_DEBUG).
+
+	  The driver applies selected sdram parameters sets in the following
+	  order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes
+	  sdram_init_detect() to complete successfully.
 
 config RAM_ROCKCHIP_LPDDR2
 	bool "LPDDR2 support for Rockchip SoCs"
 	depends on ROCKCHIP_PX30
 	help
-	  This enables LPDDR2 sdram support instead of the default DDR3 support
-	  on Rockchip SoCs.
+	  Enable LPDDR2 sdram support on Rockchip SoCs.
 
-	  Note that even if multiple DDR/LPDDR types are selected, support is
-	  enabled only for the selected one that comes first in the following
-	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+	  Note that enabling support for multiple DDR/LPDDR types may cause TPL
+	  to exceed its maximum size constraint (TPL_MAX_SIZE), depending on
+	  other configuration options selection (such as RAM_ROCKCHIP_DEBUG).
+
+	  The driver applies selected sdram parameters sets in the following
+	  order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes
+	  sdram_init_detect() to complete successfully.
 
 config RAM_ROCKCHIP_LPDDR3
 	bool "LPDDR3 support for Rockchip SoCs"
 	depends on ROCKCHIP_PX30
 	help
-	  This enables LPDDR3 sdram support instead of the default DDR3 support
+	  Enable LPDDR3 sdram support on Rockchip SoCs.
+
+	  Note that enabling support for multiple DDR/LPDDR types may cause TPL
+	  to exceed its maximum size constraint (TPL_MAX_SIZE), depending on
+	  other configuration options selection (such as RAM_ROCKCHIP_DEBUG).
+
+	  The driver applies selected sdram parameters sets in the following
+	  order - DDR4 LPDDR2 LPDDR3 DDR3 - stopping at first set that makes
+	  sdram_init_detect() to complete successfully.
+
+config RAM_ROCKCHIP_DDR4
+	bool "DDR4 support for Rockchip SoCs"
+	depends on ROCKCHIP_RV1126
+	help
+	  This enables DDR4 sdram support instead of the default DDR3 support
 	  on Rockchip SoCs.
 
 	  Note that even if multiple DDR/LPDDR types are selected, support is
 	  enabled only for the selected one that comes first in the following
-	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+	  list: LPDDR4, DDR4, DDR3.
 
 config RAM_ROCKCHIP_LPDDR4
 	depends on ROCKCHIP_RV1126
@@ -66,7 +105,7 @@ config RAM_ROCKCHIP_LPDDR4
 
 	  Note that even if multiple DDR/LPDDR types are selected, support is
 	  enabled only for the selected one that comes first in the following
-	  list: LPDDR4, DDR4, LPDDR2, LPDDR3, DDR3.
+	  list: LPDDR4, DDR4, DDR3.
 
 config RAM_ROCKCHIP_LPDDR4
 	bool "LPDDR4 support for Rockchip SoCs"
diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c
index 37e62120504..ac9f5827d1d 100644
--- a/drivers/ram/rockchip/sdram_px30.c
+++ b/drivers/ram/rockchip/sdram_px30.c
@@ -126,11 +126,17 @@ struct dram_info dram_info;
 struct px30_sdram_params sdram_configs[] = {
 #if defined(CONFIG_RAM_ROCKCHIP_DDR4)
 #include	"sdram-px30-ddr4-detect-333.inc"
-#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR2)
+#endif
+#if defined(CONFIG_RAM_ROCKCHIP_LPDDR2)
 #include	"sdram-px30-lpddr2-detect-333.inc"
-#elif defined(CONFIG_RAM_ROCKCHIP_LPDDR3)
+#endif
+#if defined(CONFIG_RAM_ROCKCHIP_LPDDR3)
 #include	"sdram-px30-lpddr3-detect-333.inc"
-#else
+#endif
+#if defined(CONFIG_RAM_ROCKCHIP_DDR3) ||         \
+	(!defined(CONFIG_RAM_ROCKCHIP_DDR4) &&   \
+	 !defined(CONFIG_RAM_ROCKCHIP_LPDDR2) && \
+	 !defined(CONFIG_RAM_ROCKCHIP_LPDDR3))
 #include	"sdram-px30-ddr3-detect-333.inc"
 #endif
 };
@@ -682,19 +688,11 @@ out:
 	return ret;
 }
 
-struct px30_sdram_params
-		*get_default_sdram_config(void)
-{
-	sdram_configs[0].skew = &skew;
-
-	return &sdram_configs[0];
-}
-
 /* return: 0 = success, other = fail */
 int sdram_init(void)
 {
 	struct px30_sdram_params *sdram_params;
-	int ret = 0;
+	int ret, i = 0;
 
 	dram_info.phy = (void *)DDR_PHY_BASE_ADDR;
 	dram_info.pctl = (void *)DDRC_BASE_ADDR;
@@ -704,12 +702,21 @@ int sdram_init(void)
 	dram_info.ddr_grf = (void *)DDR_GRF_BASE_ADDR;
 	dram_info.pmugrf = (void *)PMUGRF_BASE_ADDR;
 
-	sdram_params = get_default_sdram_config();
-	ret = sdram_init_detect(&dram_info, sdram_params);
+	do {
+		sdram_configs[i].skew = &skew;
+		sdram_params = &sdram_configs[i];
+		ret = sdram_init_detect(&dram_info, sdram_params);
+	} while (ret && ++i < ARRAY_SIZE(sdram_configs));
 
 	if (ret)
 		goto error;
 
+	if (ARRAY_SIZE(sdram_configs) > 1) {
+		printascii("Applied sdram config: ");
+		printdec(i);
+		printascii("\n");
+	}
+
 	sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base, 0);
 
 	printascii("out\n");

-- 
2.34.1