From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-arm@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Daniel Henrique Barboza" <daniel.barboza@oss.qualcomm.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Chao Liu" <chao.liu@processmission.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v5 16/21] target/riscv: Constify CPURISCVState for various cpu_*() getters
Date: Tue, 1 Sep 2026 11:52:22 +0200 [thread overview]
Message-ID: <20260901095229.72018-17-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com>
Add the const qualifier to CPURISCVState when the
argument is accessed without modification.
Simplify directly using cpu_env() in riscv_cpu_has_work().
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/riscv/cpu.h | 51 ++++++++++++++++++-----------------
target/riscv/internals.h | 2 +-
target/riscv/cpu.c | 10 +++----
target/riscv/tcg/cpu_helper.c | 18 ++++++-------
target/riscv/tcg/csr.c | 3 ++-
5 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b974c2f4b4f..eb40526f99e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -640,22 +640,22 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
uint8_t riscv_cpu_default_priority(int irq);
-uint64_t riscv_cpu_all_pending(CPURISCVState *env);
-int riscv_cpu_mirq_pending(CPURISCVState *env);
-int riscv_cpu_sirq_pending(CPURISCVState *env);
-int riscv_cpu_vsirq_pending(CPURISCVState *env);
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env);
+int riscv_cpu_mirq_pending(const CPURISCVState *env);
+int riscv_cpu_sirq_pending(const CPURISCVState *env);
+int riscv_cpu_vsirq_pending(const CPURISCVState *env);
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, const uint8_t *iprio);
-bool riscv_cpu_fp_enabled(CPURISCVState *env);
-bool riscv_cpu_vector_enabled(CPURISCVState *env);
+bool riscv_cpu_fp_enabled(const CPURISCVState *env);
+bool riscv_cpu_vector_enabled(const CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
-bool cpu_get_fcfien(CPURISCVState *env);
-bool cpu_get_bcfien(CPURISCVState *env);
-bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt);
+int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch);
+bool cpu_get_fcfien(const CPURISCVState *env);
+bool cpu_get_bcfien(const CPURISCVState *env);
+bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
@@ -685,7 +685,8 @@ void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
+RISCVException smstateen_acc_ok(const CPURISCVState *env,
+ int index, uint64_t bit);
#endif /* !CONFIG_USER_ONLY */
void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv,
@@ -750,20 +751,20 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
{
return env->misa_mxl;
}
#endif
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
-static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env)
{
return &env_archcpu(env)->cfg;
}
#if !defined(CONFIG_USER_ONLY)
-static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
+static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env)
{
privilege_mode_t mode = env->priv;
@@ -773,7 +774,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
return mode;
}
-static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
+static inline RISCVMXL cpu_get_xl(const CPURISCVState *env,
+ privilege_mode_t mode)
{
RISCVMXL xl = env->misa_mxl;
/*
@@ -801,7 +803,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env)
{
#if !defined(CONFIG_USER_ONLY)
return cpu_get_xl(env, env->priv);
@@ -814,7 +816,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
#if defined(TARGET_RISCV32)
#define cpu_address_xl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_address_xl(const CPURISCVState *env)
{
#ifdef CONFIG_USER_ONLY
return env->xl;
@@ -826,7 +828,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
}
#endif
-static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
+static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env)
{
return 16 << env->xl;
}
@@ -834,7 +836,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
#ifdef TARGET_RISCV32
#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env)
{
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
@@ -857,7 +859,8 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
* Returns true if the effective privilege mode is modified.
*/
static inline QEMU_ALWAYS_INLINE
-bool riscv_cpu_eff_priv(CPURISCVState *env, privilege_mode_t *priv, bool *virt)
+bool riscv_cpu_eff_priv(const CPURISCVState *env,
+ privilege_mode_t *priv, bool *virt)
{
privilege_mode_t mode = env->priv;
bool virt_enabled = false;
@@ -929,9 +932,9 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew,
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst);
-RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
-RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);
+bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst);
+RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env);
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
/*
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index fb2d8b3e17a..b9528209deb 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -66,7 +66,7 @@ static inline bool mmuidx_2stage(int mmu_idx)
* Return the endianness for the current privilege
* level, based on the MSTATUS MBE/SBE/UBE bits.
*/
-static inline MemOp mo_endian_env(CPURISCVState *env)
+static inline MemOp mo_endian_env(const CPURISCVState *env)
{
bool be = false;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 953e598babb..6004da4ac33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -867,7 +867,7 @@ uint8_t riscv_cpu_default_priority(int irq)
return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
};
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, const uint8_t *iprio)
{
@@ -911,7 +911,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
* using hvip bits 13:63 from HS-mode. Those are returned in
* riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending().
*/
-uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env)
{
uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
@@ -920,7 +920,7 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env)
return (env->mip | vsgein | vstip) & env->mie;
}
-int riscv_cpu_mirq_pending(CPURISCVState *env)
+int riscv_cpu_mirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
@@ -929,7 +929,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
irqs, env->miprio);
}
-int riscv_cpu_sirq_pending(CPURISCVState *env)
+int riscv_cpu_sirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
@@ -938,7 +938,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env)
irqs | irqs_f, env->siprio);
}
-int riscv_cpu_vsirq_pending(CPURISCVState *env)
+int riscv_cpu_vsirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 07d92226527..397beb356a9 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -39,7 +39,7 @@
#include "pmp.h"
#include "qemu/plugin.h"
-int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
+int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return 0;
@@ -63,7 +63,7 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
-bool cpu_get_fcfien(CPURISCVState *env)
+bool cpu_get_fcfien(const CPURISCVState *env)
{
/* no cfi extension, return false */
if (!env_archcpu(env)->cfg.ext_zicfilp) {
@@ -90,7 +90,7 @@ bool cpu_get_fcfien(CPURISCVState *env)
}
}
-bool cpu_get_bcfien(CPURISCVState *env)
+bool cpu_get_bcfien(const CPURISCVState *env)
{
/* no cfi extension, return false */
if (!env_archcpu(env)->cfg.ext_zicfiss) {
@@ -119,7 +119,7 @@ bool cpu_get_bcfien(CPURISCVState *env)
}
}
-bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
+bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt)
{
#ifdef CONFIG_USER_ONLY
return false;
@@ -163,7 +163,7 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
* M-mode: mseccfg.PMM
* Other existing modes: disabled
*/
-RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
privilege_mode_t priv_mode;
@@ -215,7 +215,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
#endif
}
-RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)
+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
privilege_mode_t priv_mode;
@@ -241,7 +241,7 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)
#endif
}
-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst)
+bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst)
{
#ifndef CONFIG_USER_ONLY
int satp_mode = 0;
@@ -426,7 +426,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
/* Return true is floating point support is currently enabled */
-bool riscv_cpu_fp_enabled(CPURISCVState *env)
+bool riscv_cpu_fp_enabled(const CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
@@ -439,7 +439,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
}
/* Return true is vector support is currently enabled */
-bool riscv_cpu_vector_enabled(CPURISCVState *env)
+bool riscv_cpu_vector_enabled(const CPURISCVState *env)
{
if (env->mstatus & MSTATUS_VS) {
if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 002f7e69c1f..f341865fb81 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -49,7 +49,8 @@ void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops)
/* Predicates */
#if !defined(CONFIG_USER_ONLY)
-RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
+RISCVException smstateen_acc_ok(const CPURISCVState *env,
+ int index, uint64_t bit)
{
bool virt = env->virt_enabled;
--
2.53.0
next prev parent reply other threads:[~2026-09-01 9:55 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
2026-09-01 11:15 ` marcandre.lureau
2026-09-03 9:50 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 02/21] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 03/21] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 04/21] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 05/21] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 11:08 ` marcandre.lureau
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 07/21] target/avr: Constify CPUAVRState for some " Philippe Mathieu-Daudé
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 12/21] target/loongarch: Constify CPULoongArchState for various tlb_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 14/21] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 15/21] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
2026-09-01 9:52 ` Philippe Mathieu-Daudé [this message]
2026-09-01 9:52 ` [PATCH v5 17/21] target/sparc: Constify CPUSPARCState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-10 19:46 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 18/21] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 19/21] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
2026-09-01 11:09 ` marcandre.lureau
2026-09-10 19:49 ` Richard Henderson
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