From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
qemu-arm@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
Subject: [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*()
Date: Tue, 1 Sep 2026 11:52:07 +0200 [thread overview]
Message-ID: <20260901095229.72018-2-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com>
Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState
argument, however here we get that argument via PTETranslate::env
so @in->env can not be const. Remove the const qualifier.
Fixes: 4a1e9d4d11c ("target/i386: Use atomic ops for pte updates")
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/i386/tcg/system/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index d7ea77c8558..44be98a3c92 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -106,7 +106,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
* even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and
* PG_DIRTY_MASK are all in the low 32 bits.
*/
-static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
+static bool ptw_setl_slow(PTETranslate *in, uint32_t old, uint32_t new)
{
uint32_t cmp;
@@ -125,7 +125,7 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
return cmp == old;
}
-static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
+static inline bool ptw_setl(PTETranslate *in, uint32_t old, uint32_t set)
{
if (set & ~old) {
uint32_t new = old | set;
--
2.53.0
next prev parent reply other threads:[~2026-09-01 9:53 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` Philippe Mathieu-Daudé [this message]
2026-09-01 11:15 ` [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*() marcandre.lureau
2026-09-03 9:50 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 02/21] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 03/21] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 04/21] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 05/21] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 11:08 ` marcandre.lureau
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 07/21] target/avr: Constify CPUAVRState for some " Philippe Mathieu-Daudé
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 12/21] target/loongarch: Constify CPULoongArchState for various tlb_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 14/21] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 15/21] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 16/21] target/riscv: Constify CPURISCVState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 17/21] target/sparc: Constify CPUSPARCState " Philippe Mathieu-Daudé
2026-09-10 19:46 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 18/21] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 19/21] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
2026-09-01 11:09 ` marcandre.lureau
2026-09-10 19:49 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260901095229.72018-2-philmd@oss.qualcomm.com \
--to=philmd@oss.qualcomm.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhao1.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.