* [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*()
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 11:15 ` marcandre.lureau
2026-09-01 9:52 ` [PATCH v5 02/21] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
` (19 subsequent siblings)
20 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé
Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState
argument, however here we get that argument via PTETranslate::env
so @in->env can not be const. Remove the const qualifier.
Fixes: 4a1e9d4d11c ("target/i386: Use atomic ops for pte updates")
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/i386/tcg/system/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index d7ea77c8558..44be98a3c92 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -106,7 +106,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
* even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and
* PG_DIRTY_MASK are all in the low 32 bits.
*/
-static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
+static bool ptw_setl_slow(PTETranslate *in, uint32_t old, uint32_t new)
{
uint32_t cmp;
@@ -125,7 +125,7 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
return cmp == old;
}
-static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
+static inline bool ptw_setl(PTETranslate *in, uint32_t old, uint32_t set)
{
if (set & ~old) {
uint32_t new = old | set;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*()
2026-09-01 9:52 ` [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
@ 2026-09-01 11:15 ` marcandre.lureau
2026-09-03 9:50 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 32+ messages in thread
From: marcandre.lureau @ 2026-09-01 11:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Paolo Bonzini, Zhao Liu, Peter Maydell,
Richard Henderson, qemu-arm
On 2026-09-01 11:52 +0200, Philippe Mathieu-Daudé wrote:
> Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState
> argument, however here we get that argument via PTETranslate::env
> so @in->env can not be const. Remove the const qualifier.
>
> Fixes: 4a1e9d4d11c ("target/i386: Use atomic ops for pte updates")
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
I think this is not really a fix, but more like a style/contract thing
anyway:
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> target/i386/tcg/system/excp_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
> index d7ea77c8558..44be98a3c92 100644
> --- a/target/i386/tcg/system/excp_helper.c
> +++ b/target/i386/tcg/system/excp_helper.c
> @@ -106,7 +106,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
> * even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and
> * PG_DIRTY_MASK are all in the low 32 bits.
> */
> -static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
> +static bool ptw_setl_slow(PTETranslate *in, uint32_t old, uint32_t new)
> {
> uint32_t cmp;
>
> @@ -125,7 +125,7 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
> return cmp == old;
> }
>
> -static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
> +static inline bool ptw_setl(PTETranslate *in, uint32_t old, uint32_t set)
> {
> if (set & ~old) {
> uint32_t new = old | set;
> --
> 2.53.0
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*()
2026-09-01 11:15 ` marcandre.lureau
@ 2026-09-03 9:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 9:50 UTC (permalink / raw)
To: marcandre.lureau
Cc: qemu-devel, Paolo Bonzini, Zhao Liu, Peter Maydell,
Richard Henderson, qemu-arm
On 1/9/26 13:15, marcandre.lureau@redhat.com wrote:
> On 2026-09-01 11:52 +0200, Philippe Mathieu-Daudé wrote:
>> Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState
>> argument, however here we get that argument via PTETranslate::env
>> so @in->env can not be const. Remove the const qualifier.
>>
>> Fixes: 4a1e9d4d11c ("target/i386: Use atomic ops for pte updates")
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>
> I think this is not really a fix, but more like a style/contract thing
Well otherwise I'm getting a build failure (discarded-qualifiers, but I
didn't record the output). I dropped that Fixes: tag, thanks!
> anyway:
> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
>
>> ---
>> target/i386/tcg/system/excp_helper.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 02/21] linux-user: Uncast void pointer argument as Object in target_cpu_free()
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 03/21] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
` (18 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Laurent Vivier,
Helge Deller, Pierrick Bouvier
init_main_thread() is registered as Object::free() hook, thus
take an Object* argument. Uncast the void pointer as such.
While now cpu_env() accept any pointer type, next commit will
restrict it to CPUState* type. QOM-cast the Object to CPU type,
otherwise we will get:
../linux-user/i386/cpu_loop.c: In function ‘target_cpu_free’:
include/hw/core/cpu.h:604:31: error: ‘_Generic’ selector of type ‘void’ is not compatible with any association
../linux-user/x86_64/../i386/cpu_loop.c:331:19: note: in expansion of macro ‘cpu_env’
331 | target_munmap(cpu_env(obj)->gdt.base,
| ^~~~~~~
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/i386/cpu_loop.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index fe922fceb5a..2f733b0b477 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -326,9 +326,10 @@ void cpu_loop(CPUX86State *env)
}
}
-static void target_cpu_free(void *obj)
+static void target_cpu_free(void *ptr)
{
- target_munmap(cpu_env(obj)->gdt.base,
+ Object *obj = ptr;
+ target_munmap(X86_CPU(obj)->env.gdt.base,
sizeof(uint64_t) * TARGET_GDT_ENTRIES);
g_free(obj);
}
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 03/21] cpus: Add const-qualified CPU environment accessors
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 01/21] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 02/21] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 04/21] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
` (17 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé,
Philippe Mathieu-Daudé, Marc-André Lureau,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Use _Generic() controlling-expression to add the const-qualified
variants of cpu_env(), env_cpu() and env_archcpu(). This allows to
safely access CPU architecture state when it should not be modified.
Alias env_cpu_const() which is still used.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
Following checkpatch.pl errors ignored:
ERROR: spaces required around that ':' (ctx:VxE)
#46: FILE: include/exec/cpu-common.h:89:
+ CPUArchState: \
^
ERROR: spaces required around that ':' (ctx:VxE)
#62: FILE: include/exec/cpu-common.h:101:
+ CPUArchState: \
^
ERROR: spaces required around that ':' (ctx:VxE)
#90: FILE: include/hw/core/cpu.h:605:
+ CPUState: \
^
total: 3 errors, 0 warnings, 64 lines checked
---
include/exec/cpu-common.h | 30 +++++++++++-------------------
include/hw/core/cpu.h | 17 ++++++++++++-----
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6594f7fa1be..60997628cc6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -85,21 +85,11 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
*
* Return the ArchCPU associated with the environment.
*/
-static inline ArchCPU *env_archcpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
-/**
- * env_cpu_const(env)
- * @env: The architecture environment
- *
- * Return the CPUState associated with the environment.
- */
-static inline const CPUState *env_cpu_const(const CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
+#define env_archcpu(env) _Generic(env, \
+ CPUArchState *: \
+ (ArchCPU *)((void *)env - sizeof(CPUState)), \
+ const CPUArchState *: \
+ (const ArchCPU *)((const void *)env - sizeof(CPUState)))
/**
* env_cpu(env)
@@ -107,9 +97,11 @@ static inline const CPUState *env_cpu_const(const CPUArchState *env)
*
* Return the CPUState associated with the environment.
*/
-static inline CPUState *env_cpu(CPUArchState *env)
-{
- return (CPUState *)env_cpu_const(env);
-}
+#define env_cpu(env) _Generic(env, \
+ CPUArchState *: \
+ (CPUState *)((void *)(env) - sizeof(CPUState)), \
+ const CPUArchState *: \
+ (const CPUState *)((const void *)(env) - sizeof(CPUState)))
+#define env_cpu_const(cpu) env_cpu(cpu)
#endif /* CPU_COMMON_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 81af7b9ee1a..18970ea39f5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -594,11 +594,18 @@ struct CPUState {
QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
-static inline CPUArchState *cpu_env(CPUState *cpu)
-{
- /* We validate that CPUArchState follows CPUState in cpu-target.c */
- return (CPUArchState *)(cpu + 1);
-}
+/**
+ * cpu_env(cpu)
+ * @cpu: The vCPU
+ *
+ * Return the CPUArchState associated with the CPU.
+ */
+#define cpu_env(cpu) _Generic(cpu, \
+ /* We validate that CPUArchState follows CPUState in target-info-stub.c */ \
+ CPUState *: \
+ (CPUArchState *)((cpu) + 1), \
+ const CPUState *: \
+ (const CPUArchState *)((cpu) + 1))
#ifdef CONFIG_TCG
/*
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 04/21] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 03/21] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 05/21] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
` (16 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé,
Philippe Mathieu-Daudé, Laurent Vivier, Helge Deller,
Pierrick Bouvier
Use the generic env_cpu() macro introduced in the previous
commit and remove the few env_cpu_const() uses.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-common.h | 1 -
linux-user/elfload.c | 2 +-
linux-user/i386/elfload.c | 2 +-
linux-user/x86_64/elfload.c | 2 +-
4 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 60997628cc6..c14362f780d 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,6 +102,5 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
(CPUState *)((void *)(env) - sizeof(CPUState)), \
const CPUArchState *: \
(const CPUState *)((const void *)(env) - sizeof(CPUState)))
-#define env_cpu_const(cpu) env_cpu(cpu)
#endif /* CPU_COMMON_H */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 88508deac50..c4bdaa146a7 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2128,7 +2128,7 @@ static int wmr_write_region(void *opaque, vaddr start,
#endif
static int elf_core_dump(int signr, const CPUArchState *env)
{
- const CPUState *cpu = env_cpu_const(env);
+ const CPUState *cpu = env_cpu(env);
const TaskState *ts = (const TaskState *)get_task_state((CPUState *)cpu);
struct rlimit dumpsize;
CountAndSizeRegions css;
diff --git a/linux-user/i386/elfload.c b/linux-user/i386/elfload.c
index 26b12001a3e..2e10f38a412 100644
--- a/linux-user/i386/elfload.c
+++ b/linux-user/i386/elfload.c
@@ -38,7 +38,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CPUX86State *env)
r->pt.es = tswapal(env->segs[R_ES].selector & 0xffff);
r->pt.fs = tswapal(env->segs[R_FS].selector & 0xffff);
r->pt.gs = tswapal(env->segs[R_GS].selector & 0xffff);
- r->pt.orig_ax = tswapal(get_task_state(env_cpu_const(env))->orig_ax);
+ r->pt.orig_ax = tswapal(get_task_state(env_cpu(env))->orig_ax);
r->pt.ip = tswapal(env->eip);
r->pt.cs = tswapal(env->segs[R_CS].selector & 0xffff);
r->pt.flags = tswapal(env->eflags);
diff --git a/linux-user/x86_64/elfload.c b/linux-user/x86_64/elfload.c
index 49a6f6180e0..121a8167acc 100644
--- a/linux-user/x86_64/elfload.c
+++ b/linux-user/x86_64/elfload.c
@@ -59,7 +59,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CPUX86State *env)
r->pt.dx = tswapal(env->regs[R_EDX]);
r->pt.si = tswapal(env->regs[R_ESI]);
r->pt.di = tswapal(env->regs[R_EDI]);
- r->pt.orig_ax = tswapal(get_task_state(env_cpu_const(env))->orig_ax);
+ r->pt.orig_ax = tswapal(get_task_state(env_cpu(env))->orig_ax);
r->pt.ip = tswapal(env->eip);
r->pt.cs = tswapal(env->segs[R_CS].selector & 0xffff);
r->pt.flags = tswapal(env->eflags);
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 05/21] system/cpus: Constify various CPUState arguments
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 04/21] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
` (15 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé,
Philippe Mathieu-Daudé
Mark the CPUState structure const when it is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 4 ++--
include/system/cpus.h | 4 ++--
system/cpus.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 18970ea39f5..328e30045ce 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -900,7 +900,7 @@ void qemu_cpu_kick(CPUState *cpu);
* Returns: %true if run state is not running or if artificially stopped;
* %false otherwise.
*/
-bool cpu_is_stopped(CPUState *cpu);
+bool cpu_is_stopped(const CPUState *cpu);
/**
* do_run_on_cpu:
@@ -1007,7 +1007,7 @@ void cpu_interrupt(CPUState *cpu, int mask);
*
* Checks if any of interrupts in @mask are pending on @cpu.
*/
-static inline bool cpu_test_interrupt(CPUState *cpu, int mask)
+static inline bool cpu_test_interrupt(const CPUState *cpu, int mask)
{
return qatomic_load_acquire(&cpu->interrupt_request) & mask;
}
diff --git a/include/system/cpus.h b/include/system/cpus.h
index 508444ccf1c..bf36b823769 100644
--- a/include/system/cpus.h
+++ b/include/system/cpus.h
@@ -13,10 +13,10 @@ const AccelOpsClass *cpus_get_accel(void);
#define VCPU_THREAD_NAME_SIZE 16
void cpus_kick_thread(CPUState *cpu);
-bool cpu_work_list_empty(CPUState *cpu);
+bool cpu_work_list_empty(const CPUState *cpu);
bool cpu_thread_is_idle(CPUState *cpu);
bool all_cpu_threads_idle(void);
-bool cpu_can_run(CPUState *cpu);
+bool cpu_can_run(const CPUState *cpu);
void qemu_process_cpu_events_common(CPUState *cpu);
void cpu_thread_signal_created(CPUState *cpu);
void cpu_thread_signal_destroyed(CPUState *cpu);
diff --git a/system/cpus.c b/system/cpus.c
index f37e215c586..e11a5aab6a6 100644
--- a/system/cpus.c
+++ b/system/cpus.c
@@ -69,12 +69,12 @@ static QemuMutex bql;
*/
static const AccelOpsClass *cpus_accel;
-bool cpu_is_stopped(CPUState *cpu)
+bool cpu_is_stopped(const CPUState *cpu)
{
return cpu->stopped || !runstate_is_running();
}
-bool cpu_work_list_empty(CPUState *cpu)
+bool cpu_work_list_empty(const CPUState *cpu)
{
return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list);
}
@@ -271,7 +271,7 @@ void cpu_interrupt(CPUState *cpu, int mask)
cpus_accel->handle_interrupt(cpu, mask);
}
-bool cpu_can_run(CPUState *cpu)
+bool cpu_can_run(const CPUState *cpu)
{
if (cpu->stop) {
return false;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 05/21] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 11:08 ` marcandre.lureau
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 07/21] target/avr: Constify CPUAVRState for some " Philippe Mathieu-Daudé
` (14 subsequent siblings)
20 siblings, 2 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé
Add the const qualifier to CPUARMState when the
argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
Ignoring one checkpatch.pl warning:
WARNING: line over 80 characters
#116: FILE: target/arm/cpu.h:2277:
+static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
total: 0 errors, 1 warnings, 789 lines checked
---
target/arm/cpu.h | 55 ++++++++++++++++----------------
target/arm/internals.h | 65 +++++++++++++++++++-------------------
target/arm/helper.c | 41 ++++++++++++------------
target/arm/tcg/debug.c | 18 +++++------
target/arm/tcg/hflags.c | 35 ++++++++++----------
target/arm/tcg/m_helper.c | 8 ++---
target/arm/tcg/op_helper.c | 2 +-
7 files changed, 114 insertions(+), 110 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e8dfc3179f2..8fc72e1c1aa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1342,9 +1342,9 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
-int fp_exception_el(CPUARMState *env, int cur_el);
-int sve_exception_el(CPUARMState *env, int cur_el);
-int sme_exception_el(CPUARMState *env, int cur_el);
+int fp_exception_el(const CPUARMState *env, int cur_el);
+int sve_exception_el(const CPUARMState *env, int cur_el);
+int sme_exception_el(const CPUARMState *env, int cur_el);
/**
* sve_vqm1_for_el_sm:
@@ -1356,10 +1356,10 @@ int sme_exception_el(CPUARMState *env, int cur_el);
* Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
* If @sm, compute for SVL, otherwise NVL.
*/
-uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
+uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm);
/* Likewise, but using @sm = PSTATE.SM. */
-uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
+uint32_t sve_vqm1_for_el(const CPUARMState *env, int el);
static inline bool is_a64(const CPUARMState *env)
{
@@ -2205,7 +2205,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
* an exception return to those levels. Unlike arm_security_space,
* this doesn't care about the current EL.
*/
-ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
+ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env);
/**
* arm_is_secure_below_el3:
@@ -2214,14 +2214,14 @@ ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
* Return true if exception levels below EL3 are in secure state,
* or would be following an exception return to those levels.
*/
-static inline bool arm_is_secure_below_el3(CPUARMState *env)
+static inline bool arm_is_secure_below_el3(const CPUARMState *env)
{
ARMSecuritySpace ss = arm_security_space_below_el3(env);
return ss == ARMSS_Secure;
}
/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
-static inline bool arm_is_el3_or_mon(CPUARMState *env)
+static inline bool arm_is_el3_or_mon(const CPUARMState *env)
{
assert(!arm_feature(env, ARM_FEATURE_M));
if (arm_feature(env, ARM_FEATURE_EL3)) {
@@ -2243,7 +2243,7 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
*
* Return the current security space of the cpu.
*/
-ARMSecuritySpace arm_security_space(CPUARMState *env);
+ARMSecuritySpace arm_security_space(const CPUARMState *env);
/**
* arm_is_secure:
@@ -2251,7 +2251,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *env);
*
* Return true if the processor is in secure state.
*/
-static inline bool arm_is_secure(CPUARMState *env)
+static inline bool arm_is_secure(const CPUARMState *env)
{
return arm_space_is_secure(arm_security_space(env));
}
@@ -2260,7 +2260,7 @@ static inline bool arm_is_secure(CPUARMState *env)
* Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
* This corresponds to the pseudocode EL2Enabled().
*/
-static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
+static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env,
ARMSecuritySpace space)
{
assert(space != ARMSS_Root);
@@ -2268,44 +2268,44 @@ static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
&& (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
}
-static inline bool arm_is_el2_enabled(CPUARMState *env)
+static inline bool arm_is_el2_enabled(const CPUARMState *env)
{
return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
}
#else
-static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
+static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
{
return ARMSS_NonSecure;
}
-static inline bool arm_is_secure_below_el3(CPUARMState *env)
+static inline bool arm_is_secure_below_el3(const CPUARMState *env)
{
return false;
}
-static inline bool arm_is_el3_or_mon(CPUARMState *env)
+static inline bool arm_is_el3_or_mon(const CPUARMState *env)
{
return false;
}
-static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
+static inline ARMSecuritySpace arm_security_space(const CPUARMState *env)
{
return ARMSS_NonSecure;
}
-static inline bool arm_is_secure(CPUARMState *env)
+static inline bool arm_is_secure(const CPUARMState *env)
{
return false;
}
-static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
+static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env,
ARMSecuritySpace space)
{
return false;
}
-static inline bool arm_is_el2_enabled(CPUARMState *env)
+static inline bool arm_is_el2_enabled(const CPUARMState *env)
{
return false;
}
@@ -2317,10 +2317,11 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
* "for all purposes other than a direct read or write access of HCR_EL2."
* Not included here is HCR_RW.
*/
-uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
-uint64_t arm_hcr_el2_eff(CPUARMState *env);
-uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env);
-uint64_t arm_hcrx_el2_eff(CPUARMState *env);
+uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env,
+ ARMSecuritySpace space);
+uint64_t arm_hcr_el2_eff(const CPUARMState *env);
+uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env);
+uint64_t arm_hcrx_el2_eff(const CPUARMState *env);
/*
* Function for determining whether guest cp register reads and writes should
@@ -2330,13 +2331,13 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env);
* it doesn't exist at all) then there is no register banking, and all
* accesses are to the non-secure version.
*/
-bool access_secure_reg(CPUARMState *env);
+bool access_secure_reg(const CPUARMState *env);
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
uint32_t cur_el, bool secure);
/* Return the highest implemented Exception Level */
-static inline int arm_highest_el(CPUARMState *env)
+static inline int arm_highest_el(const CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_EL3)) {
return 3;
@@ -2348,7 +2349,7 @@ static inline int arm_highest_el(CPUARMState *env)
}
/* Return true if a v7M CPU is in Handler mode */
-static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
+static inline bool arm_v7m_is_handler_mode(const CPUARMState *env)
{
return env->v7m.exception != 0;
}
@@ -2446,7 +2447,7 @@ static inline bool arm_sctlr_b(const CPUARMState *env)
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
}
-uint64_t arm_sctlr(CPUARMState *env, int el);
+uint64_t arm_sctlr(const CPUARMState *env, int el);
/*
* We have more than 32-bits worth of state per TB, so we split the data
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 8f44906a3be..f1a80c890ee 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -50,7 +50,7 @@
#define BANK_HYP 6
#define BANK_MON 7
-static inline MemOp mo_endian(CPUARMState *env)
+static inline MemOp mo_endian(const CPUARMState *env)
{
return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE;
}
@@ -452,14 +452,14 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
}
/* Return the effective value of SCR_EL3.RW */
-static inline bool arm_scr_rw_eff(CPUARMState *env)
+static inline bool arm_scr_rw_eff(const CPUARMState *env)
{
/*
* SCR_EL3.RW has an effective value of 1 if:
* - we are NS and EL2 is implemented but doesn't support AArch32
* - we are S and EL2 is enabled (in which case it must be AArch64)
*/
- ARMCPU *cpu = env_archcpu(env);
+ const ARMCPU *cpu = env_archcpu(env);
if (env->cp15.scr_el3 & SCR_RW) {
return true;
@@ -473,7 +473,7 @@ static inline bool arm_scr_rw_eff(CPUARMState *env)
}
/* Return true if the specified exception level is running in AArch64 state. */
-static inline bool arm_el_is_aa64(CPUARMState *env, int el)
+static inline bool arm_el_is_aa64(const CPUARMState *env, int el)
{
/*
* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
@@ -510,7 +510,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
* Return the current Exception Level (as per ARMv8; note that this differs
* from the ARMv7 Privilege Level).
*/
-static inline int arm_current_el(CPUARMState *env)
+static inline int arm_current_el(const CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_M)) {
return arm_v7m_is_handler_mode(env) ||
@@ -538,7 +538,7 @@ static inline int arm_current_el(CPUARMState *env)
}
}
-static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
+static inline bool arm_cpu_data_is_big_endian_a32(const CPUARMState *env,
bool sctlr_b)
{
#ifdef CONFIG_USER_ONLY
@@ -568,7 +568,7 @@ static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
}
/* Return true if the processor is in big-endian mode. */
-static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
+static inline bool arm_cpu_data_is_big_endian(const CPUARMState *env)
{
if (!is_a64(env)) {
return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
@@ -580,7 +580,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
#ifdef CONFIG_USER_ONLY
-static inline bool arm_cpu_bswap_data(CPUARMState *env)
+static inline bool arm_cpu_bswap_data(const CPUARMState *env)
{
return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
}
@@ -1036,7 +1036,7 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
}
/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate);
/*
* Return true if the stage 1 translation regime is using LPAE
@@ -1078,7 +1078,7 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
}
/* Return the SCTLR value which controls this address translation regime */
-static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
+static inline uint64_t regime_sctlr(const CPUARMState *env, ARMMMUIdx mmu_idx)
{
return env->cp15.sctlr_el[regime_el(mmu_idx)];
}
@@ -1094,7 +1094,7 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
R_VTCR_DS_MASK)
/* Return the value of the TCR controlling this translation regime */
-static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
+static inline uint64_t regime_tcr(const CPUARMState *env, ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_Stage2) {
return env->cp15.vtcr_el2;
@@ -1116,7 +1116,8 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
}
/* Return true if the translation regime is using LPAE format page tables */
-static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
+static inline bool regime_using_lpae_format(const CPUARMState *env,
+ ARMMMUIdx mmu_idx)
{
int el = regime_el(mmu_idx);
if (el == 2 || arm_el_is_aa64(env, el)) {
@@ -1138,7 +1139,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
* Note that the ID register BRPS field is "number of bps - 1",
* and we return the actual number of breakpoints.
*/
-static inline int arm_num_brps(ARMCPU *cpu)
+static inline int arm_num_brps(const ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1;
@@ -1152,7 +1153,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
* Note that the ID register WRPS field is "number of wps - 1",
* and we return the actual number of watchpoints.
*/
-static inline int arm_num_wrps(ARMCPU *cpu)
+static inline int arm_num_wrps(const ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1;
@@ -1166,7 +1167,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
* Note that the ID register CTX_CMPS field is "number of cmps - 1",
* and we return the actual number of comparators.
*/
-static inline int arm_num_ctx_cmps(ARMCPU *cpu)
+static inline int arm_num_ctx_cmps(const ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1;
@@ -1180,7 +1181,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
* Return true if the CPU is currently using the process stack
* pointer, or false if it is using the main stack pointer.
*/
-static inline bool v7m_using_psp(CPUARMState *env)
+static inline bool v7m_using_psp(const CPUARMState *env)
{
/* Handler mode always uses the main stack; for thread mode
* the CONTROL.SPSEL bit determines the answer.
@@ -1196,7 +1197,7 @@ static inline bool v7m_using_psp(CPUARMState *env)
* Return the SP limit value for the current CPU security state
* and stack pointer.
*/
-static inline uint32_t v7m_sp_limit(CPUARMState *env)
+static inline uint32_t v7m_sp_limit(const CPUARMState *env)
{
if (v7m_using_psp(env)) {
return env->v7m.psplim[env->v7m.secure];
@@ -1210,7 +1211,7 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
* Return true if the v7M CPACR permits access to the FPU for the specified
* security state and privilege level.
*/
-static inline bool v7m_cpacr_pass(CPUARMState *env,
+static inline bool v7m_cpacr_pass(const CPUARMState *env,
bool is_secure, bool is_priv)
{
switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
@@ -1300,7 +1301,7 @@ void arm_cpu_update_vserr(ARMCPU *cpu);
*
* Return the full ARMMMUIdx for the translation regime for EL.
*/
-ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
+ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el);
/**
* arm_mmu_idx:
@@ -1308,7 +1309,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
*
* Return the full ARMMMUIdx for the current translation regime.
*/
-ARMMMUIdx arm_mmu_idx(CPUARMState *env);
+ARMMMUIdx arm_mmu_idx(const CPUARMState *env);
/**
* arm_stage1_mmu_idx:
@@ -1463,7 +1464,7 @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
/* Determine if allocation tags are available. */
-static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
+static inline bool allocation_tag_access_enabled(const CPUARMState *env, int el,
uint64_t sctlr)
{
if (el < 3
@@ -1772,9 +1773,9 @@ enum MVEECIState {
#define PMCCFILTR_M PMXEVTYPER_M
#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
-static inline uint32_t pmu_num_counters(CPUARMState *env)
+static inline uint32_t pmu_num_counters(const CPUARMState *env)
{
- ARMCPU *cpu = env_archcpu(env);
+ const ARMCPU *cpu = env_archcpu(env);
return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
}
@@ -1814,7 +1815,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled);
void aarch64_host_initfn(Object *obj);
/* Return true if the gdbstub is presenting an AArch64 CPU */
-static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
+static inline bool arm_gdbstub_is_aarch64(const ARMCPU *cpu)
{
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
}
@@ -1832,13 +1833,13 @@ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
bool threadmode, bool spsel);
-bool el_is_in_host(CPUARMState *env, int el);
+bool el_is_in_host(const CPUARMState *env, int el);
void aa32_max_features(ARMCPU *cpu);
void aarch32_max_tcg_init(ARMCPU *cpu);
-int exception_target_el(CPUARMState *env);
-bool arm_singlestep_active(CPUARMState *env);
-bool arm_generate_debug_exceptions(CPUARMState *env);
+int exception_target_el(const CPUARMState *env);
+bool arm_singlestep_active(const CPUARMState *env);
+bool arm_generate_debug_exceptions(const CPUARMState *env);
/**
* pauth_ptr_mask:
@@ -1847,7 +1848,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env);
* Return a mask of the address bits that contain the authentication code,
* given the MMU config defined by @param.
*/
-static inline uint64_t pauth_ptr_mask(ARMVAParameters param)
+static inline uint64_t pauth_ptr_mask(const ARMVAParameters param)
{
int bot_pac_bit = 64 - param.tsz;
int top_pac_bit = 64 - 8 * param.tbi;
@@ -1903,7 +1904,7 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
* Return the maximum SVE/SME VQ for this CPU. This defines
* the maximum possible size of the Zn vector registers.
*/
-static inline int arm_max_vq(ARMCPU *cpu)
+static inline int arm_max_vq(const ARMCPU *cpu)
{
return MAX(cpu->sve_max_vq, cpu->sme_max_vq);
}
@@ -1911,7 +1912,7 @@ static inline int arm_max_vq(ARMCPU *cpu)
/*
* Return true if it is possible to take a fine-grained-trap to EL2.
*/
-static inline bool arm_fgt_active(CPUARMState *env, int el)
+static inline bool arm_fgt_active(const CPUARMState *env, int el)
{
/*
* The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
@@ -2011,7 +2012,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *env);
* specified by mask changing to the values in val.
*/
void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask);
-bool arm_pan_enabled(CPUARMState *env);
+bool arm_pan_enabled(const CPUARMState *env);
uint32_t cpsr_read_for_spsr_elx(CPUARMState *env);
void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4f30a94ecd3..0b7cf021e47 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -283,7 +283,7 @@ void arm_init_cpreg_list(ARMCPU *cpu)
}
}
-bool arm_pan_enabled(CPUARMState *env)
+bool arm_pan_enabled(const CPUARMState *env)
{
if (is_a64(env)) {
if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1)) {
@@ -3915,7 +3915,8 @@ static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
* Bits that are not included here:
* RW (read from SCR_EL3.RW as needed)
*/
-uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space)
+uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env,
+ ARMSecuritySpace space)
{
uint64_t ret = env->cp15.hcr_el2;
@@ -3980,7 +3981,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space)
return ret;
}
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
+uint64_t arm_hcr_el2_eff(const CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_M)) {
return 0;
@@ -3988,7 +3989,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env));
}
-uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env)
+uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env)
{
uint64_t hcr = arm_hcr_el2_eff(env);
@@ -4001,7 +4002,7 @@ uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env)
/*
* Corresponds to ARM pseudocode function ELIsInHost().
*/
-bool el_is_in_host(CPUARMState *env, int el)
+bool el_is_in_host(const CPUARMState *env, int el)
{
uint64_t mask;
@@ -4099,7 +4100,7 @@ static const ARMCPRegInfo hcrx_el2_reginfo = {
};
/* Return the effective value of HCRX_EL2. */
-uint64_t arm_hcrx_el2_eff(CPUARMState *env)
+uint64_t arm_hcrx_el2_eff(const CPUARMState *env)
{
/*
* The bits in this register behave as 0 for all purposes other than
@@ -4113,7 +4114,7 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)
* This may need to be revisited for future bits.
*/
if (!arm_is_el2_enabled(env)) {
- ARMCPU *cpu = env_archcpu(env);
+ const ARMCPU *cpu = env_archcpu(env);
uint64_t hcrx = 0;
/* Bits which whose effective value is 1 if el2 not enabled. */
@@ -4721,7 +4722,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
* pseudocode does *not* separate out the FP trap checks, but has them
* all in one function.
*/
-int sve_exception_el(CPUARMState *env, int el)
+int sve_exception_el(const CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1 && !el_is_in_host(env, el)) {
@@ -4770,7 +4771,7 @@ int sve_exception_el(CPUARMState *env, int el)
* Return the exception level to which exceptions should be taken for SME.
* C.f. the ARM pseudocode function CheckSMEAccess.
*/
-int sme_exception_el(CPUARMState *env, int el)
+int sme_exception_el(const CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1 && !el_is_in_host(env, el)) {
@@ -4818,10 +4819,10 @@ int sme_exception_el(CPUARMState *env, int el)
/*
* Given that SVE or SME is enabled, return the vector length for EL.
*/
-uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm)
+uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm)
{
- ARMCPU *cpu = env_archcpu(env);
- uint64_t *cr = env->vfp.zcr_el;
+ const ARMCPU *cpu = env_archcpu(env);
+ const uint64_t *cr = env->vfp.zcr_el;
uint32_t map = cpu->sve_vq.map;
uint32_t len = ARM_MAX_VQ - 1;
@@ -4856,7 +4857,7 @@ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm)
return ctz32(cpu->sme_vq.map);
}
-uint32_t sve_vqm1_for_el(CPUARMState *env, int el)
+uint32_t sve_vqm1_for_el(const CPUARMState *env, int el)
{
return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM));
}
@@ -9748,7 +9749,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-uint64_t arm_sctlr(CPUARMState *env, int el)
+uint64_t arm_sctlr(const CPUARMState *env, int el)
{
/* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */
if (el == 0) {
@@ -10072,7 +10073,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
* Return the exception level to which FP-disabled exceptions should
* be taken, or 0 if FP is enabled.
*/
-int fp_exception_el(CPUARMState *env, int cur_el)
+int fp_exception_el(const CPUARMState *env, int cur_el)
{
#ifndef CONFIG_USER_ONLY
uint64_t hcr_el2;
@@ -10179,13 +10180,13 @@ int fp_exception_el(CPUARMState *env, int cur_el)
}
#ifndef CONFIG_TCG
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
{
g_assert_not_reached();
}
#endif
-ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
+ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el)
{
ARMMMUIdx idx;
uint64_t hcr;
@@ -10238,7 +10239,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
return idx;
}
-ARMMMUIdx arm_mmu_idx(CPUARMState *env)
+ARMMMUIdx arm_mmu_idx(const CPUARMState *env)
{
return arm_mmu_idx_el(env, arm_current_el(env));
}
@@ -10359,7 +10360,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
}
#ifndef CONFIG_USER_ONLY
-ARMSecuritySpace arm_security_space(CPUARMState *env)
+ARMSecuritySpace arm_security_space(const CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_M)) {
return arm_secure_to_space(env->v7m.secure);
@@ -10391,7 +10392,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *env)
return arm_security_space_below_el3(env);
}
-ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
+ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
{
assert(!arm_feature(env, ARM_FEATURE_M));
diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c
index 528d2889c3a..af800917dea 100644
--- a/target/arm/tcg/debug.c
+++ b/target/arm/tcg/debug.c
@@ -16,7 +16,7 @@
#include "system/tcg.h"
/* Return the Exception Level targeted by debug exceptions. */
-static int arm_debug_target_el(CPUARMState *env)
+static int arm_debug_target_el(const CPUARMState *env)
{
bool secure = arm_is_secure(env);
bool route_to_el2 = false;
@@ -61,7 +61,7 @@ raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
}
/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
-static bool aa64_generate_debug_exceptions(CPUARMState *env)
+static bool aa64_generate_debug_exceptions(const CPUARMState *env)
{
int cur_el = arm_current_el(env);
int debug_el;
@@ -91,7 +91,7 @@ static bool aa64_generate_debug_exceptions(CPUARMState *env)
return debug_el > cur_el;
}
-static bool aa32_generate_debug_exceptions(CPUARMState *env)
+static bool aa32_generate_debug_exceptions(const CPUARMState *env)
{
int el = arm_current_el(env);
@@ -145,7 +145,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env)
* CheckSoftwareStep(), where it is elided because both branches would
* always return the same value.
*/
-bool arm_generate_debug_exceptions(CPUARMState *env)
+bool arm_generate_debug_exceptions(const CPUARMState *env)
{
if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) {
return false;
@@ -161,7 +161,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env)
* Is single-stepping active? (Note that the "is EL_D AArch64?" check
* implicitly means this always returns false in pre-v8 CPUs.)
*/
-bool arm_singlestep_active(CPUARMState *env)
+bool arm_singlestep_active(const CPUARMState *env)
{
return extract32(env->cp15.mdscr_el1, 0, 1)
&& arm_el_is_aa64(env, arm_debug_target_el(env))
@@ -169,9 +169,9 @@ bool arm_singlestep_active(CPUARMState *env)
}
/* Return true if the linked breakpoint entry lbn passes its checks */
-static bool linked_bp_matches(ARMCPU *cpu, int lbn)
+static bool linked_bp_matches(const ARMCPU *cpu, int lbn)
{
- CPUARMState *env = &cpu->env;
+ const CPUARMState *env = &cpu->env;
uint64_t bcr = env->cp15.dbgbcr[lbn];
int brps = arm_num_brps(cpu);
int ctx_cmps = arm_num_ctx_cmps(cpu);
@@ -252,9 +252,9 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
}
-static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
+static bool bp_wp_matches(const ARMCPU *cpu, int n, bool is_wp)
{
- CPUARMState *env = &cpu->env;
+ const CPUARMState *env = &cpu->env;
uint64_t cr;
int pac, hmc, ssc, wt, lbn;
/*
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index 296ec8101ab..ec837794287 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -14,7 +14,7 @@
#include "accel/tcg/cpu-ops.h"
#include "cpregs.h"
-static inline bool fgt_svc(CPUARMState *env, int el)
+static inline bool fgt_svc(const CPUARMState *env, int el)
{
/*
* Assuming fine-grained-traps are active, return true if we
@@ -29,7 +29,8 @@ static inline bool fgt_svc(CPUARMState *env, int el)
}
/* Return true if memory alignment should be enforced. */
-static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
+static bool aprofile_require_alignment(const CPUARMState *env,
+ int el, uint64_t sctlr)
{
#ifdef CONFIG_USER_ONLY
return false;
@@ -65,7 +66,7 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
#endif
}
-bool access_secure_reg(CPUARMState *env)
+bool access_secure_reg(const CPUARMState *env)
{
bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3) &&
@@ -74,7 +75,7 @@ bool access_secure_reg(CPUARMState *env)
return ret;
}
-static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
+static CPUARMTBFlags rebuild_hflags_common(const CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx,
CPUARMTBFlags flags)
{
@@ -88,7 +89,7 @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
return flags;
}
-static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
+static CPUARMTBFlags rebuild_hflags_common_32(const CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx,
CPUARMTBFlags flags)
{
@@ -105,7 +106,7 @@ static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
-static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
+static CPUARMTBFlags rebuild_hflags_m32(const CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx)
{
CPUARMTBFlags flags = {};
@@ -139,7 +140,7 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
}
/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
-static bool sme_fa64(CPUARMState *env, int el)
+static bool sme_fa64(const CPUARMState *env, int el)
{
if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
return false;
@@ -164,7 +165,7 @@ static bool sme_fa64(CPUARMState *env, int el)
return true;
}
-static int neon_exception_el(CPUARMState *env, int cur_el)
+static int neon_exception_el(const CPUARMState *env, int cur_el)
{
/*
* Return the EL to trap to for A32 Neon specific traps
@@ -244,7 +245,7 @@ static int neon_exception_el(CPUARMState *env, int cur_el)
return 0;
}
-static bool arm_d32dis(CPUARMState *env, int cur_el)
+static bool arm_d32dis(const CPUARMState *env, int cur_el)
{
bool cpacr_d32dis = FIELD_EX64(env->cp15.cpacr_el1, CPACR, D32DIS);
@@ -262,7 +263,7 @@ static bool arm_d32dis(CPUARMState *env, int cur_el)
return cpacr_d32dis;
}
-static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
+static CPUARMTBFlags rebuild_hflags_a32(const CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx)
{
CPUARMTBFlags flags = {};
@@ -318,7 +319,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
* Return the exception level to which exceptions should be taken for ZT0.
* C.f. the ARM pseudocode function CheckSMEZT0Enabled, after the ZA check.
*/
-static int zt0_exception_el(CPUARMState *env, int el)
+static int zt0_exception_el(const CPUARMState *env, int el)
{
#ifndef CONFIG_USER_ONLY
if (el <= 1
@@ -344,7 +345,7 @@ static int zt0_exception_el(CPUARMState *env, int el)
* Compare the EnFPM bits in the "Accessing FPMR" pseudocode. Note that
* the floating-point enabled check will be handled separately.
*/
-static int fpmr_exception_el(CPUARMState *env, int el)
+static int fpmr_exception_el(const CPUARMState *env, int el)
{
switch (el) {
case 0:
@@ -377,8 +378,8 @@ static int fpmr_exception_el(CPUARMState *env, int el)
return 0;
}
-static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
- ARMMMUIdx mmu_idx)
+static CPUARMTBFlags rebuild_hflags_a64(const CPUARMState *env, int el,
+ int fp_el, ARMMMUIdx mmu_idx)
{
CPUARMTBFlags flags = {};
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
@@ -664,7 +665,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
-static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
+static CPUARMTBFlags rebuild_hflags_internal(const CPUARMState *env)
{
int el = arm_current_el(env);
int fp_el = fp_exception_el(env, el);
@@ -733,7 +734,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
}
-static void assert_hflags_rebuild_correctly(CPUARMState *env)
+static void assert_hflags_rebuild_correctly(const CPUARMState *env)
{
#ifdef CONFIG_DEBUG_TCG
CPUARMTBFlags c = env->hflags;
@@ -749,7 +750,7 @@ static void assert_hflags_rebuild_correctly(CPUARMState *env)
#endif
}
-static bool mve_no_pred(CPUARMState *env)
+static bool mve_no_pred(const CPUARMState *env)
{
/*
* Return true if there is definitely no predication of MVE
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index f4ba93b291b..09084154bdd 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -156,14 +156,14 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
return 0;
}
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
{
return ARMMMUIdx_MUser;
}
#else /* !CONFIG_USER_ONLY */
-static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+static ARMMMUIdx arm_v7m_mmu_idx_all(const CPUARMState *env,
bool secstate, bool priv, bool negpri)
{
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
@@ -183,7 +183,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
return mmu_idx;
}
-static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(const CPUARMState *env,
bool secstate, bool priv)
{
bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
@@ -192,7 +192,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
}
/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
{
bool priv = arm_v7m_is_handler_mode(env) ||
!(env->v7m.control[secstate] & 1);
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 857e897a48d..8de3a6fdad5 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -30,7 +30,7 @@
#define SIGNBIT (uint32_t)0x80000000
#define SIGNBIT64 ((uint64_t)1 << 63)
-int exception_target_el(CPUARMState *env)
+int exception_target_el(const CPUARMState *env)
{
int target_el = MAX(1, arm_current_el(env));
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 11:08 ` marcandre.lureau
2026-09-10 19:44 ` Richard Henderson
1 sibling, 0 replies; 32+ messages in thread
From: marcandre.lureau @ 2026-09-01 11:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Paolo Bonzini, Zhao Liu, Peter Maydell,
Richard Henderson, qemu-arm
On 2026-09-01 11:52 +0200, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to CPUARMState when the
> argument is accessed without modification.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> Ignoring one checkpatch.pl warning:
>
> WARNING: line over 80 characters
> #116: FILE: target/arm/cpu.h:2277:
> +static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
>
> total: 0 errors, 1 warnings, 789 lines checked
> ---
> target/arm/cpu.h | 55 ++++++++++++++++----------------
> target/arm/internals.h | 65 +++++++++++++++++++-------------------
> target/arm/helper.c | 41 ++++++++++++------------
> target/arm/tcg/debug.c | 18 +++++------
> target/arm/tcg/hflags.c | 35 ++++++++++----------
> target/arm/tcg/m_helper.c | 8 ++---
> target/arm/tcg/op_helper.c | 2 +-
> 7 files changed, 114 insertions(+), 110 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e8dfc3179f2..8fc72e1c1aa 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1342,9 +1342,9 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
> void aarch64_sync_32_to_64(CPUARMState *env);
> void aarch64_sync_64_to_32(CPUARMState *env);
>
> -int fp_exception_el(CPUARMState *env, int cur_el);
> -int sve_exception_el(CPUARMState *env, int cur_el);
> -int sme_exception_el(CPUARMState *env, int cur_el);
> +int fp_exception_el(const CPUARMState *env, int cur_el);
> +int sve_exception_el(const CPUARMState *env, int cur_el);
> +int sme_exception_el(const CPUARMState *env, int cur_el);
>
> /**
> * sve_vqm1_for_el_sm:
> @@ -1356,10 +1356,10 @@ int sme_exception_el(CPUARMState *env, int cur_el);
> * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
> * If @sm, compute for SVL, otherwise NVL.
> */
> -uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
> +uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm);
>
> /* Likewise, but using @sm = PSTATE.SM. */
> -uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
> +uint32_t sve_vqm1_for_el(const CPUARMState *env, int el);
>
> static inline bool is_a64(const CPUARMState *env)
> {
> @@ -2205,7 +2205,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
> * an exception return to those levels. Unlike arm_security_space,
> * this doesn't care about the current EL.
> */
> -ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
> +ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env);
>
> /**
> * arm_is_secure_below_el3:
> @@ -2214,14 +2214,14 @@ ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
> * Return true if exception levels below EL3 are in secure state,
> * or would be following an exception return to those levels.
> */
> -static inline bool arm_is_secure_below_el3(CPUARMState *env)
> +static inline bool arm_is_secure_below_el3(const CPUARMState *env)
> {
> ARMSecuritySpace ss = arm_security_space_below_el3(env);
> return ss == ARMSS_Secure;
> }
>
> /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
> -static inline bool arm_is_el3_or_mon(CPUARMState *env)
> +static inline bool arm_is_el3_or_mon(const CPUARMState *env)
> {
> assert(!arm_feature(env, ARM_FEATURE_M));
> if (arm_feature(env, ARM_FEATURE_EL3)) {
> @@ -2243,7 +2243,7 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
> *
> * Return the current security space of the cpu.
> */
> -ARMSecuritySpace arm_security_space(CPUARMState *env);
> +ARMSecuritySpace arm_security_space(const CPUARMState *env);
>
> /**
> * arm_is_secure:
> @@ -2251,7 +2251,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *env);
> *
> * Return true if the processor is in secure state.
> */
> -static inline bool arm_is_secure(CPUARMState *env)
> +static inline bool arm_is_secure(const CPUARMState *env)
> {
> return arm_space_is_secure(arm_security_space(env));
> }
> @@ -2260,7 +2260,7 @@ static inline bool arm_is_secure(CPUARMState *env)
> * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
> * This corresponds to the pseudocode EL2Enabled().
> */
> -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
> +static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env,
> ARMSecuritySpace space)
> {
> assert(space != ARMSS_Root);
> @@ -2268,44 +2268,44 @@ static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
> && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
> }
>
> -static inline bool arm_is_el2_enabled(CPUARMState *env)
> +static inline bool arm_is_el2_enabled(const CPUARMState *env)
> {
> return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
> }
>
> #else
> -static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
> +static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
> {
> return ARMSS_NonSecure;
> }
>
> -static inline bool arm_is_secure_below_el3(CPUARMState *env)
> +static inline bool arm_is_secure_below_el3(const CPUARMState *env)
> {
> return false;
> }
>
> -static inline bool arm_is_el3_or_mon(CPUARMState *env)
> +static inline bool arm_is_el3_or_mon(const CPUARMState *env)
> {
> return false;
> }
>
> -static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
> +static inline ARMSecuritySpace arm_security_space(const CPUARMState *env)
> {
> return ARMSS_NonSecure;
> }
>
> -static inline bool arm_is_secure(CPUARMState *env)
> +static inline bool arm_is_secure(const CPUARMState *env)
> {
> return false;
> }
>
> -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
> +static inline bool arm_is_el2_enabled_secstate(const CPUARMState *env,
> ARMSecuritySpace space)
> {
> return false;
> }
>
> -static inline bool arm_is_el2_enabled(CPUARMState *env)
> +static inline bool arm_is_el2_enabled(const CPUARMState *env)
> {
> return false;
> }
> @@ -2317,10 +2317,11 @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
> * "for all purposes other than a direct read or write access of HCR_EL2."
> * Not included here is HCR_RW.
> */
> -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
> -uint64_t arm_hcr_el2_eff(CPUARMState *env);
> -uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env);
> -uint64_t arm_hcrx_el2_eff(CPUARMState *env);
> +uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env,
> + ARMSecuritySpace space);
> +uint64_t arm_hcr_el2_eff(const CPUARMState *env);
> +uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env);
> +uint64_t arm_hcrx_el2_eff(const CPUARMState *env);
>
> /*
> * Function for determining whether guest cp register reads and writes should
> @@ -2330,13 +2331,13 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env);
> * it doesn't exist at all) then there is no register banking, and all
> * accesses are to the non-secure version.
> */
> -bool access_secure_reg(CPUARMState *env);
> +bool access_secure_reg(const CPUARMState *env);
>
> uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
> uint32_t cur_el, bool secure);
>
> /* Return the highest implemented Exception Level */
> -static inline int arm_highest_el(CPUARMState *env)
> +static inline int arm_highest_el(const CPUARMState *env)
> {
> if (arm_feature(env, ARM_FEATURE_EL3)) {
> return 3;
> @@ -2348,7 +2349,7 @@ static inline int arm_highest_el(CPUARMState *env)
> }
>
> /* Return true if a v7M CPU is in Handler mode */
> -static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
> +static inline bool arm_v7m_is_handler_mode(const CPUARMState *env)
> {
> return env->v7m.exception != 0;
> }
> @@ -2446,7 +2447,7 @@ static inline bool arm_sctlr_b(const CPUARMState *env)
> (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
> }
>
> -uint64_t arm_sctlr(CPUARMState *env, int el);
> +uint64_t arm_sctlr(const CPUARMState *env, int el);
>
> /*
> * We have more than 32-bits worth of state per TB, so we split the data
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 8f44906a3be..f1a80c890ee 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -50,7 +50,7 @@
> #define BANK_HYP 6
> #define BANK_MON 7
>
> -static inline MemOp mo_endian(CPUARMState *env)
> +static inline MemOp mo_endian(const CPUARMState *env)
> {
> return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE;
> }
> @@ -452,14 +452,14 @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
> }
>
> /* Return the effective value of SCR_EL3.RW */
> -static inline bool arm_scr_rw_eff(CPUARMState *env)
> +static inline bool arm_scr_rw_eff(const CPUARMState *env)
> {
> /*
> * SCR_EL3.RW has an effective value of 1 if:
> * - we are NS and EL2 is implemented but doesn't support AArch32
> * - we are S and EL2 is enabled (in which case it must be AArch64)
> */
> - ARMCPU *cpu = env_archcpu(env);
> + const ARMCPU *cpu = env_archcpu(env);
>
> if (env->cp15.scr_el3 & SCR_RW) {
> return true;
> @@ -473,7 +473,7 @@ static inline bool arm_scr_rw_eff(CPUARMState *env)
> }
>
> /* Return true if the specified exception level is running in AArch64 state. */
> -static inline bool arm_el_is_aa64(CPUARMState *env, int el)
> +static inline bool arm_el_is_aa64(const CPUARMState *env, int el)
> {
> /*
> * This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
> @@ -510,7 +510,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
> * Return the current Exception Level (as per ARMv8; note that this differs
> * from the ARMv7 Privilege Level).
> */
> -static inline int arm_current_el(CPUARMState *env)
> +static inline int arm_current_el(const CPUARMState *env)
> {
> if (arm_feature(env, ARM_FEATURE_M)) {
> return arm_v7m_is_handler_mode(env) ||
> @@ -538,7 +538,7 @@ static inline int arm_current_el(CPUARMState *env)
> }
> }
>
> -static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
> +static inline bool arm_cpu_data_is_big_endian_a32(const CPUARMState *env,
> bool sctlr_b)
> {
> #ifdef CONFIG_USER_ONLY
> @@ -568,7 +568,7 @@ static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
> }
>
> /* Return true if the processor is in big-endian mode. */
> -static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
> +static inline bool arm_cpu_data_is_big_endian(const CPUARMState *env)
> {
> if (!is_a64(env)) {
> return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
> @@ -580,7 +580,7 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
> }
>
> #ifdef CONFIG_USER_ONLY
> -static inline bool arm_cpu_bswap_data(CPUARMState *env)
> +static inline bool arm_cpu_bswap_data(const CPUARMState *env)
> {
> return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
> }
> @@ -1036,7 +1036,7 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
> }
>
> /* Return the MMU index for a v7M CPU in the specified security state */
> -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
> +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate);
>
> /*
> * Return true if the stage 1 translation regime is using LPAE
> @@ -1078,7 +1078,7 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
> }
>
> /* Return the SCTLR value which controls this address translation regime */
> -static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
> +static inline uint64_t regime_sctlr(const CPUARMState *env, ARMMMUIdx mmu_idx)
> {
> return env->cp15.sctlr_el[regime_el(mmu_idx)];
> }
> @@ -1094,7 +1094,7 @@ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
> R_VTCR_DS_MASK)
>
> /* Return the value of the TCR controlling this translation regime */
> -static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
> +static inline uint64_t regime_tcr(const CPUARMState *env, ARMMMUIdx mmu_idx)
> {
> if (mmu_idx == ARMMMUIdx_Stage2) {
> return env->cp15.vtcr_el2;
> @@ -1116,7 +1116,8 @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
> }
>
> /* Return true if the translation regime is using LPAE format page tables */
> -static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
> +static inline bool regime_using_lpae_format(const CPUARMState *env,
> + ARMMMUIdx mmu_idx)
> {
> int el = regime_el(mmu_idx);
> if (el == 2 || arm_el_is_aa64(env, el)) {
> @@ -1138,7 +1139,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
> * Note that the ID register BRPS field is "number of bps - 1",
> * and we return the actual number of breakpoints.
> */
> -static inline int arm_num_brps(ARMCPU *cpu)
> +static inline int arm_num_brps(const ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1;
> @@ -1152,7 +1153,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
> * Note that the ID register WRPS field is "number of wps - 1",
> * and we return the actual number of watchpoints.
> */
> -static inline int arm_num_wrps(ARMCPU *cpu)
> +static inline int arm_num_wrps(const ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1;
> @@ -1166,7 +1167,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
> * Note that the ID register CTX_CMPS field is "number of cmps - 1",
> * and we return the actual number of comparators.
> */
> -static inline int arm_num_ctx_cmps(ARMCPU *cpu)
> +static inline int arm_num_ctx_cmps(const ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1;
> @@ -1180,7 +1181,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
> * Return true if the CPU is currently using the process stack
> * pointer, or false if it is using the main stack pointer.
> */
> -static inline bool v7m_using_psp(CPUARMState *env)
> +static inline bool v7m_using_psp(const CPUARMState *env)
> {
> /* Handler mode always uses the main stack; for thread mode
> * the CONTROL.SPSEL bit determines the answer.
> @@ -1196,7 +1197,7 @@ static inline bool v7m_using_psp(CPUARMState *env)
> * Return the SP limit value for the current CPU security state
> * and stack pointer.
> */
> -static inline uint32_t v7m_sp_limit(CPUARMState *env)
> +static inline uint32_t v7m_sp_limit(const CPUARMState *env)
> {
> if (v7m_using_psp(env)) {
> return env->v7m.psplim[env->v7m.secure];
> @@ -1210,7 +1211,7 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
> * Return true if the v7M CPACR permits access to the FPU for the specified
> * security state and privilege level.
> */
> -static inline bool v7m_cpacr_pass(CPUARMState *env,
> +static inline bool v7m_cpacr_pass(const CPUARMState *env,
> bool is_secure, bool is_priv)
> {
> switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
> @@ -1300,7 +1301,7 @@ void arm_cpu_update_vserr(ARMCPU *cpu);
> *
> * Return the full ARMMMUIdx for the translation regime for EL.
> */
> -ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
> +ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el);
>
> /**
> * arm_mmu_idx:
> @@ -1308,7 +1309,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
> *
> * Return the full ARMMMUIdx for the current translation regime.
> */
> -ARMMMUIdx arm_mmu_idx(CPUARMState *env);
> +ARMMMUIdx arm_mmu_idx(const CPUARMState *env);
>
> /**
> * arm_stage1_mmu_idx:
> @@ -1463,7 +1464,7 @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
> int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
>
> /* Determine if allocation tags are available. */
> -static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
> +static inline bool allocation_tag_access_enabled(const CPUARMState *env, int el,
> uint64_t sctlr)
> {
> if (el < 3
> @@ -1772,9 +1773,9 @@ enum MVEECIState {
> #define PMCCFILTR_M PMXEVTYPER_M
> #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
>
> -static inline uint32_t pmu_num_counters(CPUARMState *env)
> +static inline uint32_t pmu_num_counters(const CPUARMState *env)
> {
> - ARMCPU *cpu = env_archcpu(env);
> + const ARMCPU *cpu = env_archcpu(env);
>
> return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
> }
> @@ -1814,7 +1815,7 @@ void aarch64_aa32_a57_init(ARMCPU *cpu, bool aa64_enabled);
> void aarch64_host_initfn(Object *obj);
>
> /* Return true if the gdbstub is presenting an AArch64 CPU */
> -static inline bool arm_gdbstub_is_aarch64(ARMCPU *cpu)
> +static inline bool arm_gdbstub_is_aarch64(const ARMCPU *cpu)
> {
> return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
> }
> @@ -1832,13 +1833,13 @@ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
> uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
> bool threadmode, bool spsel);
>
> -bool el_is_in_host(CPUARMState *env, int el);
> +bool el_is_in_host(const CPUARMState *env, int el);
>
> void aa32_max_features(ARMCPU *cpu);
> void aarch32_max_tcg_init(ARMCPU *cpu);
> -int exception_target_el(CPUARMState *env);
> -bool arm_singlestep_active(CPUARMState *env);
> -bool arm_generate_debug_exceptions(CPUARMState *env);
> +int exception_target_el(const CPUARMState *env);
> +bool arm_singlestep_active(const CPUARMState *env);
> +bool arm_generate_debug_exceptions(const CPUARMState *env);
>
> /**
> * pauth_ptr_mask:
> @@ -1847,7 +1848,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env);
> * Return a mask of the address bits that contain the authentication code,
> * given the MMU config defined by @param.
> */
> -static inline uint64_t pauth_ptr_mask(ARMVAParameters param)
> +static inline uint64_t pauth_ptr_mask(const ARMVAParameters param)
> {
> int bot_pac_bit = 64 - param.tsz;
> int top_pac_bit = 64 - 8 * param.tbi;
> @@ -1903,7 +1904,7 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
> * Return the maximum SVE/SME VQ for this CPU. This defines
> * the maximum possible size of the Zn vector registers.
> */
> -static inline int arm_max_vq(ARMCPU *cpu)
> +static inline int arm_max_vq(const ARMCPU *cpu)
> {
> return MAX(cpu->sve_max_vq, cpu->sme_max_vq);
> }
> @@ -1911,7 +1912,7 @@ static inline int arm_max_vq(ARMCPU *cpu)
> /*
> * Return true if it is possible to take a fine-grained-trap to EL2.
> */
> -static inline bool arm_fgt_active(CPUARMState *env, int el)
> +static inline bool arm_fgt_active(const CPUARMState *env, int el)
> {
> /*
> * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
> @@ -2011,7 +2012,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *env);
> * specified by mask changing to the values in val.
> */
> void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask);
> -bool arm_pan_enabled(CPUARMState *env);
> +bool arm_pan_enabled(const CPUARMState *env);
> uint32_t cpsr_read_for_spsr_elx(CPUARMState *env);
> void cpsr_write_from_spsr_elx(CPUARMState *env, uint32_t val);
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 4f30a94ecd3..0b7cf021e47 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -283,7 +283,7 @@ void arm_init_cpreg_list(ARMCPU *cpu)
> }
> }
>
> -bool arm_pan_enabled(CPUARMState *env)
> +bool arm_pan_enabled(const CPUARMState *env)
> {
> if (is_a64(env)) {
> if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) == (HCR_NV | HCR_NV1)) {
> @@ -3915,7 +3915,8 @@ static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
> * Bits that are not included here:
> * RW (read from SCR_EL3.RW as needed)
> */
> -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space)
> +uint64_t arm_hcr_el2_eff_secstate(const CPUARMState *env,
> + ARMSecuritySpace space)
> {
> uint64_t ret = env->cp15.hcr_el2;
>
> @@ -3980,7 +3981,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space)
> return ret;
> }
>
> -uint64_t arm_hcr_el2_eff(CPUARMState *env)
> +uint64_t arm_hcr_el2_eff(const CPUARMState *env)
> {
> if (arm_feature(env, ARM_FEATURE_M)) {
> return 0;
> @@ -3988,7 +3989,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
> return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env));
> }
>
> -uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env)
> +uint64_t arm_hcr_el2_nvx_eff(const CPUARMState *env)
> {
> uint64_t hcr = arm_hcr_el2_eff(env);
>
> @@ -4001,7 +4002,7 @@ uint64_t arm_hcr_el2_nvx_eff(CPUARMState *env)
> /*
> * Corresponds to ARM pseudocode function ELIsInHost().
> */
> -bool el_is_in_host(CPUARMState *env, int el)
> +bool el_is_in_host(const CPUARMState *env, int el)
> {
> uint64_t mask;
>
> @@ -4099,7 +4100,7 @@ static const ARMCPRegInfo hcrx_el2_reginfo = {
> };
>
> /* Return the effective value of HCRX_EL2. */
> -uint64_t arm_hcrx_el2_eff(CPUARMState *env)
> +uint64_t arm_hcrx_el2_eff(const CPUARMState *env)
> {
> /*
> * The bits in this register behave as 0 for all purposes other than
> @@ -4113,7 +4114,7 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)
> * This may need to be revisited for future bits.
> */
> if (!arm_is_el2_enabled(env)) {
> - ARMCPU *cpu = env_archcpu(env);
> + const ARMCPU *cpu = env_archcpu(env);
> uint64_t hcrx = 0;
>
> /* Bits which whose effective value is 1 if el2 not enabled. */
> @@ -4721,7 +4722,7 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
> * pseudocode does *not* separate out the FP trap checks, but has them
> * all in one function.
> */
> -int sve_exception_el(CPUARMState *env, int el)
> +int sve_exception_el(const CPUARMState *env, int el)
> {
> #ifndef CONFIG_USER_ONLY
> if (el <= 1 && !el_is_in_host(env, el)) {
> @@ -4770,7 +4771,7 @@ int sve_exception_el(CPUARMState *env, int el)
> * Return the exception level to which exceptions should be taken for SME.
> * C.f. the ARM pseudocode function CheckSMEAccess.
> */
> -int sme_exception_el(CPUARMState *env, int el)
> +int sme_exception_el(const CPUARMState *env, int el)
> {
> #ifndef CONFIG_USER_ONLY
> if (el <= 1 && !el_is_in_host(env, el)) {
> @@ -4818,10 +4819,10 @@ int sme_exception_el(CPUARMState *env, int el)
> /*
> * Given that SVE or SME is enabled, return the vector length for EL.
> */
> -uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm)
> +uint32_t sve_vqm1_for_el_sm(const CPUARMState *env, int el, bool sm)
> {
> - ARMCPU *cpu = env_archcpu(env);
> - uint64_t *cr = env->vfp.zcr_el;
> + const ARMCPU *cpu = env_archcpu(env);
> + const uint64_t *cr = env->vfp.zcr_el;
> uint32_t map = cpu->sve_vq.map;
> uint32_t len = ARM_MAX_VQ - 1;
>
> @@ -4856,7 +4857,7 @@ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm)
> return ctz32(cpu->sme_vq.map);
> }
>
> -uint32_t sve_vqm1_for_el(CPUARMState *env, int el)
> +uint32_t sve_vqm1_for_el(const CPUARMState *env, int el)
> {
> return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM));
> }
> @@ -9748,7 +9749,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -uint64_t arm_sctlr(CPUARMState *env, int el)
> +uint64_t arm_sctlr(const CPUARMState *env, int el)
> {
> /* Only EL0 needs to be adjusted for EL1&0 or EL2&0 or EL3&0 */
> if (el == 0) {
> @@ -10072,7 +10073,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
> * Return the exception level to which FP-disabled exceptions should
> * be taken, or 0 if FP is enabled.
> */
> -int fp_exception_el(CPUARMState *env, int cur_el)
> +int fp_exception_el(const CPUARMState *env, int cur_el)
> {
> #ifndef CONFIG_USER_ONLY
> uint64_t hcr_el2;
> @@ -10179,13 +10180,13 @@ int fp_exception_el(CPUARMState *env, int cur_el)
> }
>
> #ifndef CONFIG_TCG
> -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
> +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
> {
> g_assert_not_reached();
> }
> #endif
>
> -ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
> +ARMMMUIdx arm_mmu_idx_el(const CPUARMState *env, int el)
> {
> ARMMMUIdx idx;
> uint64_t hcr;
> @@ -10238,7 +10239,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
> return idx;
> }
>
> -ARMMMUIdx arm_mmu_idx(CPUARMState *env)
> +ARMMMUIdx arm_mmu_idx(const CPUARMState *env)
> {
> return arm_mmu_idx_el(env, arm_current_el(env));
> }
> @@ -10359,7 +10360,7 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
> }
>
> #ifndef CONFIG_USER_ONLY
> -ARMSecuritySpace arm_security_space(CPUARMState *env)
> +ARMSecuritySpace arm_security_space(const CPUARMState *env)
> {
> if (arm_feature(env, ARM_FEATURE_M)) {
> return arm_secure_to_space(env->v7m.secure);
> @@ -10391,7 +10392,7 @@ ARMSecuritySpace arm_security_space(CPUARMState *env)
> return arm_security_space_below_el3(env);
> }
>
> -ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
> +ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
> {
> assert(!arm_feature(env, ARM_FEATURE_M));
>
> diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c
> index 528d2889c3a..af800917dea 100644
> --- a/target/arm/tcg/debug.c
> +++ b/target/arm/tcg/debug.c
> @@ -16,7 +16,7 @@
> #include "system/tcg.h"
>
> /* Return the Exception Level targeted by debug exceptions. */
> -static int arm_debug_target_el(CPUARMState *env)
> +static int arm_debug_target_el(const CPUARMState *env)
> {
> bool secure = arm_is_secure(env);
> bool route_to_el2 = false;
> @@ -61,7 +61,7 @@ raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
> }
>
> /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
> -static bool aa64_generate_debug_exceptions(CPUARMState *env)
> +static bool aa64_generate_debug_exceptions(const CPUARMState *env)
> {
> int cur_el = arm_current_el(env);
> int debug_el;
> @@ -91,7 +91,7 @@ static bool aa64_generate_debug_exceptions(CPUARMState *env)
> return debug_el > cur_el;
> }
>
> -static bool aa32_generate_debug_exceptions(CPUARMState *env)
> +static bool aa32_generate_debug_exceptions(const CPUARMState *env)
> {
> int el = arm_current_el(env);
>
> @@ -145,7 +145,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env)
> * CheckSoftwareStep(), where it is elided because both branches would
> * always return the same value.
> */
> -bool arm_generate_debug_exceptions(CPUARMState *env)
> +bool arm_generate_debug_exceptions(const CPUARMState *env)
> {
> if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) {
> return false;
> @@ -161,7 +161,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env)
> * Is single-stepping active? (Note that the "is EL_D AArch64?" check
> * implicitly means this always returns false in pre-v8 CPUs.)
> */
> -bool arm_singlestep_active(CPUARMState *env)
> +bool arm_singlestep_active(const CPUARMState *env)
> {
> return extract32(env->cp15.mdscr_el1, 0, 1)
> && arm_el_is_aa64(env, arm_debug_target_el(env))
> @@ -169,9 +169,9 @@ bool arm_singlestep_active(CPUARMState *env)
> }
>
> /* Return true if the linked breakpoint entry lbn passes its checks */
> -static bool linked_bp_matches(ARMCPU *cpu, int lbn)
> +static bool linked_bp_matches(const ARMCPU *cpu, int lbn)
> {
> - CPUARMState *env = &cpu->env;
> + const CPUARMState *env = &cpu->env;
> uint64_t bcr = env->cp15.dbgbcr[lbn];
> int brps = arm_num_brps(cpu);
> int ctx_cmps = arm_num_ctx_cmps(cpu);
> @@ -252,9 +252,9 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
> return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
> }
>
> -static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
> +static bool bp_wp_matches(const ARMCPU *cpu, int n, bool is_wp)
> {
> - CPUARMState *env = &cpu->env;
> + const CPUARMState *env = &cpu->env;
> uint64_t cr;
> int pac, hmc, ssc, wt, lbn;
> /*
> diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
> index 296ec8101ab..ec837794287 100644
> --- a/target/arm/tcg/hflags.c
> +++ b/target/arm/tcg/hflags.c
> @@ -14,7 +14,7 @@
> #include "accel/tcg/cpu-ops.h"
> #include "cpregs.h"
>
> -static inline bool fgt_svc(CPUARMState *env, int el)
> +static inline bool fgt_svc(const CPUARMState *env, int el)
> {
> /*
> * Assuming fine-grained-traps are active, return true if we
> @@ -29,7 +29,8 @@ static inline bool fgt_svc(CPUARMState *env, int el)
> }
>
> /* Return true if memory alignment should be enforced. */
> -static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
> +static bool aprofile_require_alignment(const CPUARMState *env,
> + int el, uint64_t sctlr)
> {
> #ifdef CONFIG_USER_ONLY
> return false;
> @@ -65,7 +66,7 @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
> #endif
> }
>
> -bool access_secure_reg(CPUARMState *env)
> +bool access_secure_reg(const CPUARMState *env)
> {
> bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
> !arm_el_is_aa64(env, 3) &&
> @@ -74,7 +75,7 @@ bool access_secure_reg(CPUARMState *env)
> return ret;
> }
>
> -static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
> +static CPUARMTBFlags rebuild_hflags_common(const CPUARMState *env, int fp_el,
> ARMMMUIdx mmu_idx,
> CPUARMTBFlags flags)
> {
> @@ -88,7 +89,7 @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
> return flags;
> }
>
> -static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
> +static CPUARMTBFlags rebuild_hflags_common_32(const CPUARMState *env, int fp_el,
> ARMMMUIdx mmu_idx,
> CPUARMTBFlags flags)
> {
> @@ -105,7 +106,7 @@ static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
> return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
> }
>
> -static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
> +static CPUARMTBFlags rebuild_hflags_m32(const CPUARMState *env, int fp_el,
> ARMMMUIdx mmu_idx)
> {
> CPUARMTBFlags flags = {};
> @@ -139,7 +140,7 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
> }
>
> /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
> -static bool sme_fa64(CPUARMState *env, int el)
> +static bool sme_fa64(const CPUARMState *env, int el)
> {
> if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
> return false;
> @@ -164,7 +165,7 @@ static bool sme_fa64(CPUARMState *env, int el)
> return true;
> }
>
> -static int neon_exception_el(CPUARMState *env, int cur_el)
> +static int neon_exception_el(const CPUARMState *env, int cur_el)
> {
> /*
> * Return the EL to trap to for A32 Neon specific traps
> @@ -244,7 +245,7 @@ static int neon_exception_el(CPUARMState *env, int cur_el)
> return 0;
> }
>
> -static bool arm_d32dis(CPUARMState *env, int cur_el)
> +static bool arm_d32dis(const CPUARMState *env, int cur_el)
> {
> bool cpacr_d32dis = FIELD_EX64(env->cp15.cpacr_el1, CPACR, D32DIS);
>
> @@ -262,7 +263,7 @@ static bool arm_d32dis(CPUARMState *env, int cur_el)
> return cpacr_d32dis;
> }
>
> -static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
> +static CPUARMTBFlags rebuild_hflags_a32(const CPUARMState *env, int fp_el,
> ARMMMUIdx mmu_idx)
> {
> CPUARMTBFlags flags = {};
> @@ -318,7 +319,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
> * Return the exception level to which exceptions should be taken for ZT0.
> * C.f. the ARM pseudocode function CheckSMEZT0Enabled, after the ZA check.
> */
> -static int zt0_exception_el(CPUARMState *env, int el)
> +static int zt0_exception_el(const CPUARMState *env, int el)
> {
> #ifndef CONFIG_USER_ONLY
> if (el <= 1
> @@ -344,7 +345,7 @@ static int zt0_exception_el(CPUARMState *env, int el)
> * Compare the EnFPM bits in the "Accessing FPMR" pseudocode. Note that
> * the floating-point enabled check will be handled separately.
> */
> -static int fpmr_exception_el(CPUARMState *env, int el)
> +static int fpmr_exception_el(const CPUARMState *env, int el)
> {
> switch (el) {
> case 0:
> @@ -377,8 +378,8 @@ static int fpmr_exception_el(CPUARMState *env, int el)
> return 0;
> }
>
> -static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
> - ARMMMUIdx mmu_idx)
> +static CPUARMTBFlags rebuild_hflags_a64(const CPUARMState *env, int el,
> + int fp_el, ARMMMUIdx mmu_idx)
> {
> CPUARMTBFlags flags = {};
> ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
> @@ -664,7 +665,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
> return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
> }
>
> -static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
> +static CPUARMTBFlags rebuild_hflags_internal(const CPUARMState *env)
> {
> int el = arm_current_el(env);
> int fp_el = fp_exception_el(env, el);
> @@ -733,7 +734,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
> env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
> }
>
> -static void assert_hflags_rebuild_correctly(CPUARMState *env)
> +static void assert_hflags_rebuild_correctly(const CPUARMState *env)
> {
> #ifdef CONFIG_DEBUG_TCG
> CPUARMTBFlags c = env->hflags;
> @@ -749,7 +750,7 @@ static void assert_hflags_rebuild_correctly(CPUARMState *env)
> #endif
> }
>
> -static bool mve_no_pred(CPUARMState *env)
> +static bool mve_no_pred(const CPUARMState *env)
> {
> /*
> * Return true if there is definitely no predication of MVE
> diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
> index f4ba93b291b..09084154bdd 100644
> --- a/target/arm/tcg/m_helper.c
> +++ b/target/arm/tcg/m_helper.c
> @@ -156,14 +156,14 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
> return 0;
> }
>
> -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
> +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
> {
> return ARMMMUIdx_MUser;
> }
>
> #else /* !CONFIG_USER_ONLY */
>
> -static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
> +static ARMMMUIdx arm_v7m_mmu_idx_all(const CPUARMState *env,
> bool secstate, bool priv, bool negpri)
> {
> ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
> @@ -183,7 +183,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
> return mmu_idx;
> }
>
> -static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
> +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(const CPUARMState *env,
> bool secstate, bool priv)
> {
> bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
> @@ -192,7 +192,7 @@ static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
> }
>
> /* Return the MMU index for a v7M CPU in the specified security state */
> -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
> +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(const CPUARMState *env, bool secstate)
> {
> bool priv = arm_v7m_is_handler_mode(env) ||
> !(env->v7m.control[secstate] & 1);
> diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
> index 857e897a48d..8de3a6fdad5 100644
> --- a/target/arm/tcg/op_helper.c
> +++ b/target/arm/tcg/op_helper.c
> @@ -30,7 +30,7 @@
> #define SIGNBIT (uint32_t)0x80000000
> #define SIGNBIT64 ((uint64_t)1 << 63)
>
> -int exception_target_el(CPUARMState *env)
> +int exception_target_el(const CPUARMState *env)
> {
> int target_el = MAX(1, arm_current_el(env));
>
> --
> 2.53.0
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
2026-09-01 11:08 ` marcandre.lureau
@ 2026-09-10 19:44 ` Richard Henderson
1 sibling, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, qemu-arm
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to CPUARMState when the
> argument is accessed without modification.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> ---
> Ignoring one checkpatch.pl warning:
>
> WARNING: line over 80 characters
> #116: FILE: target/arm/cpu.h:2277:
> +static inline ARMSecuritySpace arm_security_space_below_el3(const CPUARMState *env)
>
> total: 0 errors, 1 warnings, 789 lines checked
> ---
> target/arm/cpu.h | 55 ++++++++++++++++----------------
> target/arm/internals.h | 65 +++++++++++++++++++-------------------
> target/arm/helper.c | 41 ++++++++++++------------
> target/arm/tcg/debug.c | 18 +++++------
> target/arm/tcg/hflags.c | 35 ++++++++++----------
> target/arm/tcg/m_helper.c | 8 ++---
> target/arm/tcg/op_helper.c | 2 +-
> 7 files changed, 114 insertions(+), 110 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 07/21] target/avr: Constify CPUAVRState for some cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 06/21] target/arm: Constify CPUARMState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-10 19:44 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
` (13 subsequent siblings)
20 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Michael Rolnik
Add the const qualifier to CPUAVRState when the
argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/avr/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index a818db753b2..1e4e839bd83 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int avr_print_insn(bfd_vma addr, disassemble_info *info);
vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
-static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
+static inline int avr_feature(const CPUAVRState *env, AVRFeature feature)
{
return (env->features & (1U << feature)) != 0;
}
@@ -204,12 +204,12 @@ enum {
TB_FLAGS_SKIP = 2,
};
-static inline int cpu_interrupts_enabled(CPUAVRState *env)
+static inline int cpu_interrupts_enabled(const CPUAVRState *env)
{
return env->sregI != 0;
}
-static inline uint8_t cpu_get_sreg(CPUAVRState *env)
+static inline uint8_t cpu_get_sreg(const CPUAVRState *env)
{
return (env->sregC) << 0
| (env->sregZ) << 1
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 07/21] target/avr: Constify CPUAVRState for some cpu_*() getters
2026-09-01 9:52 ` [PATCH v5 07/21] target/avr: Constify CPUAVRState for some " Philippe Mathieu-Daudé
@ 2026-09-10 19:44 ` Richard Henderson
0 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, qemu-arm,
Marc-André Lureau, Michael Rolnik
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to CPUAVRState when the
> argument is accessed without modification.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> Reviewed-by: Marc-André Lureau<marcandre.lureau@redhat.com>
> ---
> target/avr/cpu.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 07/21] target/avr: Constify CPUAVRState for some " Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
` (12 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Brian Cain, Pierrick Bouvier
@env argument is accessed without modification in
hexagon_thread_is_enabled(), qualify it as const.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/cpu.h | 2 +-
target/hexagon/cpu_helper.h | 4 ++--
target/hexagon/cpu.c | 4 ++--
target/hexagon/cpu_helper.c | 6 +++---
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index c50fbb3f72a..e4f120eda17 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
* @return true if the @a thread_env hardware thread is
* not stopped.
*/
-bool hexagon_thread_is_enabled(CPUHexagonState *thread_env);
+bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env);
uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg);
void hexagon_cpu_soft_reset(CPUHexagonState *env);
#endif
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index d1767503156..a669091a89d 100644
--- a/target/hexagon/cpu_helper.h
+++ b/target/hexagon/cpu_helper.h
@@ -9,8 +9,8 @@
uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);
void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old);
-int get_cpu_mode(CPUHexagonState *env);
-int get_exe_mode(CPUHexagonState *env);
+int get_cpu_mode(const CPUHexagonState *env);
+int get_exe_mode(const CPUHexagonState *env);
void clear_wait_mode(CPUHexagonState *env);
void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause);
void hexagon_start_threads(CPUHexagonState *env, uint32_t mask);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 9765716b516..4cc6bd67c28 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-bool hexagon_thread_is_enabled(CPUHexagonState *env)
+bool hexagon_thread_is_enabled(const CPUHexagonState *env)
{
- HexagonCPU *cpu = env_archcpu(env);
+ const HexagonCPU *cpu = env_archcpu(env);
uint32_t modectl;
uint32_t thread_enabled_mask;
bool E_bit;
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index 64c5746c6d9..610e29a0503 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -212,9 +212,9 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause)
}
-int get_exe_mode(CPUHexagonState *env)
+int get_exe_mode(const CPUHexagonState *env)
{
- HexagonCPU *cpu;
+ const HexagonCPU *cpu;
uint32_t modectl, thread_enabled_mask, thread_wait_mask;
uint32_t isdbst, debugmode;
bool E_bit, W_bit, D_bit;
@@ -384,7 +384,7 @@ static int sys_in_user_mode_ssr(uint32_t ssr)
return 0;
}
-int get_cpu_mode(CPUHexagonState *env)
+int get_cpu_mode(const CPUHexagonState *env)
{
uint32_t ssr = env->t_sreg[HEX_SREG_SSR];
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
` (11 subsequent siblings)
20 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau
x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled()
only read CPU state without modification, add the const
qualifiers to CPUState and CPUX86State parameters.
Simplify directly using cpu_env() in x86_cpu_pending_interrupt.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/i386/cpu.h | 4 ++--
target/i386/cpu.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 641f3ee5c2f..b0436dbf665 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2596,7 +2596,7 @@ void x86_cpu_gdb_init(CPUState *cs);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
#ifndef CONFIG_USER_ONLY
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request);
bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr,
TranslateForDebugResult *result);
@@ -3104,7 +3104,7 @@ static inline bool ctl_has_irq(CPUX86State *env)
return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
}
-static inline bool x86_cpu_interrupts_enabled(CPUX86State *env)
+static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env)
{
return ((env->eflags & IF_MASK) &&
!(env->hflags & HF_INHIBIT_IRQ_MASK)) ||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5ffb10d156..1fc02cf94e6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10601,10 +10601,9 @@ static vaddr x86_cpu_get_pc(CPUState *cs)
}
#if !defined(CONFIG_USER_ONLY)
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
+ const CPUX86State *env = cpu_env(cs);
if (interrupt_request & CPU_INTERRUPT_POLL) {
return CPU_INTERRUPT_POLL;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters
2026-09-01 9:52 ` [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
@ 2026-09-10 19:45 ` Richard Henderson
0 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, qemu-arm,
Marc-André Lureau
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled()
> only read CPU state without modification, add the const
> qualifiers to CPUState and CPUX86State parameters.
> Simplify directly using cpu_env() in x86_cpu_pending_interrupt.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> Reviewed-by: Marc-André Lureau<marcandre.lureau@redhat.com>
> ---
> target/i386/cpu.h | 4 ++--
> target/i386/cpu.c | 5 ++---
> 2 files changed, 4 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 09/21] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Philippe Mathieu-Daudé
` (10 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Bibo Mao, Song Gao,
Xianglai Li
The pointed LoongArchTLB is only read, not modified: mark it const.
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/loongarch/tcg/tlb_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index a4b90beca65..40cc0764248 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -238,11 +238,11 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
* field in tlb entry contains bit[47:13], so need adjust.
* virt_vpn = vaddr[47:13]
*/
-static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env,
- vaddr vaddr, int csr_asid,
- tlb_match func)
+static const LoongArchTLB *
+loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
+ int csr_asid, tlb_match func)
{
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
uint16_t tlb_asid, stlb_idx;
uint8_t tlb_e, tlb_ps, stlb_ps;
bool tlb_g;
@@ -296,7 +296,7 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
{
int csr_asid;
tlb_match func;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
CPUSysState *sys = env_sys(env);
func = tlb_match_any;
@@ -594,7 +594,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_asid;
@@ -608,7 +608,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
target_ulong info, target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_any;
@@ -842,7 +842,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
MMUAccessType access_type, int index,
int mmu_idx)
{
- LoongArchTLB *tlb = &env->tlb[index];
+ const LoongArchTLB *tlb = &env->tlb[index];
uint8_t tlb_ps, n;
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 10/21] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 12/21] target/loongarch: Constify CPULoongArchState for various tlb_*() getters Philippe Mathieu-Daudé
` (9 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Bibo Mao, Song Gao, Xianglai Li
Add the const qualifier to CPULoongArchState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu.h | 6 +++---
target/loongarch/internals.h | 2 +-
target/loongarch/cpu.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 97db3b453fe..ad8e7497279 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -486,7 +486,7 @@ struct LoongArchCPUClass {
#define MMU_USER_IDX MMU_PLV_USER
#define MMU_DA_IDX 4
-static inline CPUSysState *env_sys(CPULoongArchState *env)
+static inline CPUSysState *env_sys(const CPULoongArchState *env)
{
return env->sys_state;
}
@@ -496,12 +496,12 @@ static inline void set_sys_state(CPULoongArchState *env, CPUSysState *sys)
env->sys_state = sys;
}
-static inline bool is_la64(CPULoongArchState *env)
+static inline bool is_la64(const CPULoongArchState *env)
{
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
}
-static inline bool is_va32(CPULoongArchState *env)
+static inline bool is_va32(const CPULoongArchState *env)
{
/* VA32 if !LA64 or VA32L[1-3] */
bool va32 = !is_la64(env);
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 5e9a6c7bd65..a831507f439 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
uint64_t value);
-bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env);
+bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env);
#endif /* !CONFIG_USER_ONLY */
uint64_t read_fcc(CPULoongArchState *env);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 7b601bd3728..3b3cbde882f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -96,7 +96,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
}
/* Check if there is pending and not masked out interrupt */
-bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
+bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env)
{
uint32_t pending;
uint32_t status;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 12/21] target/loongarch: Constify CPULoongArchState for various tlb_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
` (8 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Bibo Mao, Song Gao,
Xianglai Li
Add the const qualifier to CPULoongArchState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 20 ++++++++++----------
target/loongarch/tcg/tcg_loongarch.h | 2 +-
target/loongarch/cpu_helper.c | 20 ++++++++++----------
target/loongarch/tcg/tlb_helper.c | 12 ++++++------
4 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index 54fb732d62d..61b59f3d3f3 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -30,14 +30,14 @@ typedef struct MMUContext {
uint64_t pte_buddy[2];
} MMUContext;
-static inline bool cpu_has_ptw(CPULoongArchState *env)
+static inline bool cpu_has_ptw(const CPULoongArchState *env)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
return !!FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, HPTW_EN);
}
-static inline bool pte_present(CPULoongArchState *env, uint64_t entry)
+static inline bool pte_present(const CPULoongArchState *env, uint64_t entry)
{
uint8_t present;
@@ -50,7 +50,7 @@ static inline bool pte_present(CPULoongArchState *env, uint64_t entry)
return !!present;
}
-static inline bool pte_write(CPULoongArchState *env, uint64_t entry)
+static inline bool pte_write(const CPULoongArchState *env, uint64_t entry)
{
uint8_t writable;
@@ -89,17 +89,17 @@ static inline bool pte_dirty(uint64_t entry)
return !!FIELD_EX64(entry, TLBENTRY, D);
}
-bool check_ps(CPULoongArchState *ent, uint8_t ps);
-TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+bool check_ps(const CPULoongArchState *ent, uint8_t ps);
+TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx);
-TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
+TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug);
-TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context,
int access_type, int mmu_idx, int debug);
-void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, unsigned int level);
hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
-uint64_t loongarch_palen_mask(CPULoongArchState *env);
+uint64_t loongarch_palen_mask(const CPULoongArchState *env);
#endif /* LOONGARCH_CPU_MMU_H */
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
index 7fb627f2d63..0f20c60d73d 100644
--- a/target/loongarch/tcg/tcg_loongarch.h
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -16,7 +16,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx);
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 123cad3d930..3401e7ed727 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -18,10 +18,10 @@
#include "cpu-mmu.h"
#include "tcg/tcg_loongarch.h"
-void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, unsigned int level)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
switch (level) {
case 1:
@@ -48,7 +48,7 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
}
}
-TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx)
{
uint64_t plv = mmu_idx;
@@ -111,7 +111,7 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
return TLBRET_MATCH;
}
-static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys,
+static MemTxResult loongarch_cmpxchg_phys(const CPUState *cs, hwaddr phys,
uint64_t old, uint64_t new)
{
hwaddr addr1, l = 8;
@@ -146,11 +146,11 @@ static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys,
return ret;
}
-TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context,
int access_type, int mmu_idx, int debug)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- CPUState *cs = env_cpu(env);
+ const CPUState *cs = env_cpu(env);
hwaddr index = 0, phys = 0;
uint64_t palen_mask = loongarch_palen_mask(env);
uint64_t dir_base, dir_width;
@@ -273,7 +273,7 @@ restart:
return ret;
}
-static TLBRet loongarch_map_address(CPULoongArchState *env,
+static TLBRet loongarch_map_address(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
@@ -299,7 +299,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *env,
return TLBRET_NOMATCH;
}
-static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw)
+static hwaddr dmw_va2pa(const CPULoongArchState *env, vaddr va, uint64_t dmw)
{
if (is_la64(env)) {
return va & TARGET_VIRT_MASK;
@@ -310,7 +310,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw)
}
}
-TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
+TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
@@ -376,7 +376,7 @@ hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
return context.physical;
}
-uint64_t loongarch_palen_mask(CPULoongArchState *env)
+uint64_t loongarch_palen_mask(const CPULoongArchState *env)
{
/* PALEN stores physical address bits - 1 */
uint64_t phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN) + 1;
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 40cc0764248..6194b976c36 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -35,9 +35,9 @@ static bool tlb_match_asid(bool global, int asid, int tlb_asid)
return !global && tlb_asid == asid;
}
-bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
+bool check_ps(const CPULoongArchState *env, uint8_t tlb_ps)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
if (tlb_ps >= 64) {
return false;
@@ -239,7 +239,7 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
* virt_vpn = vaddr[47:13]
*/
static const LoongArchTLB *
-loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
+loongarch_tlb_search_cb(const CPULoongArchState *env, vaddr vaddr,
int csr_asid, tlb_match func)
{
const LoongArchTLB *tlb;
@@ -291,7 +291,7 @@ loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
return NULL;
}
-static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
+static bool loongarch_tlb_search(const CPULoongArchState *env, vaddr vaddr,
int *index)
{
int csr_asid;
@@ -837,7 +837,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
sys->CSR_TLBREHI = FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
}
-static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
+static TLBRet loongarch_map_tlb_entry(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int index,
int mmu_idx)
@@ -853,7 +853,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
return loongarch_check_pte(env, context, access_type, mmu_idx);
}
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx)
{
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 12/21] target/loongarch: Constify CPULoongArchState for various tlb_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-10 19:45 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 14/21] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
` (7 subsequent siblings)
20 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Philippe Mathieu-Daudé, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo
Add the const qualifier to CPUMIPSState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/mips/cpu.h | 8 ++++----
target/mips/internal.h | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 319147a948c..32549791a18 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1300,7 +1300,7 @@ static inline int hflags_mmu_index(uint32_t hflags)
}
}
-static inline int mips_env_mmu_index(CPUMIPSState *env)
+static inline int mips_env_mmu_index(const CPUMIPSState *env)
{
return hflags_mmu_index(env->hflags);
}
@@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSState *env)
}
/* Check presence of MSA implementation */
-static inline bool ase_msa_available(CPUMIPSState *env)
+static inline bool ase_msa_available(const CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MSAP);
}
/* Check presence of Loongson CSR instructions */
-static inline bool ase_lcsr_available(CPUMIPSState *env)
+static inline bool ase_lcsr_available(const CPUMIPSState *env)
{
return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
}
/* Check presence of multi-threading ASE implementation */
-static inline bool ase_mt_available(CPUMIPSState *env)
+static inline bool ase_mt_available(const CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MT);
}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index c5c286872eb..7dba22300b1 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
extern const VMStateDescription vmstate_mips_cpu;
-static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env)
{
return (env->CP0_Status & (1 << CP0St_IE)) &&
!(env->CP0_Status & (1 << CP0St_EXL)) &&
@@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
}
/* Check if there is pending and not masked out interrupt */
-static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env)
{
int32_t pending;
int32_t status;
@@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env)
}
}
-static inline int mips_vpe_active(CPUMIPSState *env)
+static inline int mips_vpe_active(const CPUMIPSState *env)
{
- MIPSCPU *cpu = env_archcpu(env);
+ const MIPSCPU *cpu = env_archcpu(env);
int active = 1;
/* Check that the VPE is enabled. */
@@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
return active;
}
-static inline int mips_vp_active(CPUMIPSState *env)
+static inline int mips_vp_active(const CPUMIPSState *env)
{
CPUState *cs;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters
2026-09-01 9:52 ` [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-10 19:45 ` Richard Henderson
0 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, qemu-arm,
Marc-André Lureau, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to CPUMIPSState when
> the argument is accessed without modification.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> Reviewed-by: Marc-André Lureau<marcandre.lureau@redhat.com>
> ---
> target/mips/cpu.h | 8 ++++----
> target/mips/internal.h | 10 +++++-----
> 2 files changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 14/21] target/s390x: Constify S390CPU for cpu_has_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 15/21] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
` (6 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Ilya Leoshkevich,
Marc-André Lureau, Eric Farman, David Hildenbrand,
Cornelia Huck, Matthew Rosato, qemu-s390x
Add the const qualifier to S390CPU when the argument
is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Eric Farman <farman@linux.ibm.com>
---
target/s390x/cpu.h | 2 +-
target/s390x/s390x-internal.h | 12 ++++++------
target/s390x/interrupt.c | 22 +++++++++++-----------
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index f55b79ef8ac..998bbb0d7ff 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
return 0;
}
#endif /* CONFIG_USER_ONLY */
-static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
+static inline uint8_t s390_cpu_get_state(const S390CPU *cpu)
{
return cpu->env.cpu_state;
}
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index c23ee1c8476..df1297b5c67 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -333,12 +333,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu);
void cpu_inject_cpu_timer(S390CPU *cpu);
void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr);
int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr);
-bool s390_cpu_has_io_int(S390CPU *cpu);
-bool s390_cpu_has_ext_int(S390CPU *cpu);
-bool s390_cpu_has_mcck_int(S390CPU *cpu);
-bool s390_cpu_has_int(S390CPU *cpu);
-bool s390_cpu_has_restart_int(S390CPU *cpu);
-bool s390_cpu_has_stop_int(S390CPU *cpu);
+bool s390_cpu_has_io_int(const S390CPU *cpu);
+bool s390_cpu_has_ext_int(const S390CPU *cpu);
+bool s390_cpu_has_mcck_int(const S390CPU *cpu);
+bool s390_cpu_has_int(const S390CPU *cpu);
+bool s390_cpu_has_restart_int(const S390CPU *cpu);
+bool s390_cpu_has_stop_int(const S390CPU *cpu);
void cpu_inject_restart(S390CPU *cpu);
void cpu_inject_stop(S390CPU *cpu);
#endif /* CONFIG_USER_ONLY */
diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c
index 1dca835c5d8..d7e3fd45e4b 100644
--- a/target/s390x/interrupt.c
+++ b/target/s390x/interrupt.c
@@ -139,10 +139,10 @@ void s390_crw_mchk(void)
fsc->inject_crw_mchk(fs);
}
-bool s390_cpu_has_mcck_int(S390CPU *cpu)
+bool s390_cpu_has_mcck_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_MCHECK)) {
return false;
@@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu)
return false;
}
-bool s390_cpu_has_ext_int(S390CPU *cpu)
+bool s390_cpu_has_ext_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_EXT)) {
return false;
@@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu)
return false;
}
-bool s390_cpu_has_io_int(S390CPU *cpu)
+bool s390_cpu_has_io_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_IO)) {
return false;
@@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu)
return qemu_s390_flic_has_io(flic, env->cregs[6]);
}
-bool s390_cpu_has_restart_int(S390CPU *cpu)
+bool s390_cpu_has_restart_int(const S390CPU *cpu)
{
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
return env->pending_int & INTERRUPT_RESTART;
}
-bool s390_cpu_has_stop_int(S390CPU *cpu)
+bool s390_cpu_has_stop_int(const S390CPU *cpu)
{
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
return env->pending_int & INTERRUPT_STOP;
}
-bool s390_cpu_has_int(S390CPU *cpu)
+bool s390_cpu_has_int(const S390CPU *cpu)
{
if (!tcg_enabled()) {
return false;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 15/21] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 14/21] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 16/21] target/riscv: Constify CPURISCVState for various cpu_*() getters Philippe Mathieu-Daudé
` (5 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, qemu-riscv
@iprio[] is an array only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 718b66487a2..b974c2f4b4f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -646,7 +646,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env);
int riscv_cpu_vsirq_pending(CPURISCVState *env);
int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
- uint64_t pending, uint8_t *iprio);
+ uint64_t pending, const uint8_t *iprio);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab68ce65e93..953e598babb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -869,7 +869,7 @@ uint8_t riscv_cpu_default_priority(int irq)
int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
- uint64_t pending, uint8_t *iprio)
+ uint64_t pending, const uint8_t *iprio)
{
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 16/21] target/riscv: Constify CPURISCVState for various cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 15/21] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 17/21] target/sparc: Constify CPUSPARCState " Philippe Mathieu-Daudé
` (4 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, qemu-riscv
Add the const qualifier to CPURISCVState when the
argument is accessed without modification.
Simplify directly using cpu_env() in riscv_cpu_has_work().
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/riscv/cpu.h | 51 ++++++++++++++++++-----------------
target/riscv/internals.h | 2 +-
target/riscv/cpu.c | 10 +++----
target/riscv/tcg/cpu_helper.c | 18 ++++++-------
target/riscv/tcg/csr.c | 3 ++-
5 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b974c2f4b4f..eb40526f99e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -640,22 +640,22 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
uint8_t riscv_cpu_default_priority(int irq);
-uint64_t riscv_cpu_all_pending(CPURISCVState *env);
-int riscv_cpu_mirq_pending(CPURISCVState *env);
-int riscv_cpu_sirq_pending(CPURISCVState *env);
-int riscv_cpu_vsirq_pending(CPURISCVState *env);
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env);
+int riscv_cpu_mirq_pending(const CPURISCVState *env);
+int riscv_cpu_sirq_pending(const CPURISCVState *env);
+int riscv_cpu_vsirq_pending(const CPURISCVState *env);
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, const uint8_t *iprio);
-bool riscv_cpu_fp_enabled(CPURISCVState *env);
-bool riscv_cpu_vector_enabled(CPURISCVState *env);
+bool riscv_cpu_fp_enabled(const CPURISCVState *env);
+bool riscv_cpu_vector_enabled(const CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
-bool cpu_get_fcfien(CPURISCVState *env);
-bool cpu_get_bcfien(CPURISCVState *env);
-bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt);
+int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch);
+bool cpu_get_fcfien(const CPURISCVState *env);
+bool cpu_get_bcfien(const CPURISCVState *env);
+bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
@@ -685,7 +685,8 @@ void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level);
void riscv_cpu_interrupt(CPURISCVState *env);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
+RISCVException smstateen_acc_ok(const CPURISCVState *env,
+ int index, uint64_t bit);
#endif /* !CONFIG_USER_ONLY */
void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv,
@@ -750,20 +751,20 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
{
return env->misa_mxl;
}
#endif
#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
-static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env)
{
return &env_archcpu(env)->cfg;
}
#if !defined(CONFIG_USER_ONLY)
-static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
+static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env)
{
privilege_mode_t mode = env->priv;
@@ -773,7 +774,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
return mode;
}
-static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
+static inline RISCVMXL cpu_get_xl(const CPURISCVState *env,
+ privilege_mode_t mode)
{
RISCVMXL xl = env->misa_mxl;
/*
@@ -801,7 +803,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env)
{
#if !defined(CONFIG_USER_ONLY)
return cpu_get_xl(env, env->priv);
@@ -814,7 +816,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
#if defined(TARGET_RISCV32)
#define cpu_address_xl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_address_xl(const CPURISCVState *env)
{
#ifdef CONFIG_USER_ONLY
return env->xl;
@@ -826,7 +828,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
}
#endif
-static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
+static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env)
{
return 16 << env->xl;
}
@@ -834,7 +836,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
#ifdef TARGET_RISCV32
#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
#else
-static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env)
{
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
@@ -857,7 +859,8 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
* Returns true if the effective privilege mode is modified.
*/
static inline QEMU_ALWAYS_INLINE
-bool riscv_cpu_eff_priv(CPURISCVState *env, privilege_mode_t *priv, bool *virt)
+bool riscv_cpu_eff_priv(const CPURISCVState *env,
+ privilege_mode_t *priv, bool *virt)
{
privilege_mode_t mode = env->priv;
bool virt_enabled = false;
@@ -929,9 +932,9 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew,
bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst);
-RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
-RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);
+bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst);
+RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env);
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
/*
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index fb2d8b3e17a..b9528209deb 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -66,7 +66,7 @@ static inline bool mmuidx_2stage(int mmu_idx)
* Return the endianness for the current privilege
* level, based on the MSTATUS MBE/SBE/UBE bits.
*/
-static inline MemOp mo_endian_env(CPURISCVState *env)
+static inline MemOp mo_endian_env(const CPURISCVState *env)
{
bool be = false;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 953e598babb..6004da4ac33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -867,7 +867,7 @@ uint8_t riscv_cpu_default_priority(int irq)
return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
};
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
uint64_t pending, const uint8_t *iprio)
{
@@ -911,7 +911,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
* using hvip bits 13:63 from HS-mode. Those are returned in
* riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending().
*/
-uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env)
{
uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
@@ -920,7 +920,7 @@ uint64_t riscv_cpu_all_pending(CPURISCVState *env)
return (env->mip | vsgein | vstip) & env->mie;
}
-int riscv_cpu_mirq_pending(CPURISCVState *env)
+int riscv_cpu_mirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
@@ -929,7 +929,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
irqs, env->miprio);
}
-int riscv_cpu_sirq_pending(CPURISCVState *env)
+int riscv_cpu_sirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
@@ -938,7 +938,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env)
irqs | irqs_f, env->siprio);
}
-int riscv_cpu_vsirq_pending(CPURISCVState *env)
+int riscv_cpu_vsirq_pending(const CPURISCVState *env)
{
uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c
index 07d92226527..397beb356a9 100644
--- a/target/riscv/tcg/cpu_helper.c
+++ b/target/riscv/tcg/cpu_helper.c
@@ -39,7 +39,7 @@
#include "pmp.h"
#include "qemu/plugin.h"
-int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
+int riscv_env_mmu_index(const CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return 0;
@@ -63,7 +63,7 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
#endif
}
-bool cpu_get_fcfien(CPURISCVState *env)
+bool cpu_get_fcfien(const CPURISCVState *env)
{
/* no cfi extension, return false */
if (!env_archcpu(env)->cfg.ext_zicfilp) {
@@ -90,7 +90,7 @@ bool cpu_get_fcfien(CPURISCVState *env)
}
}
-bool cpu_get_bcfien(CPURISCVState *env)
+bool cpu_get_bcfien(const CPURISCVState *env)
{
/* no cfi extension, return false */
if (!env_archcpu(env)->cfg.ext_zicfiss) {
@@ -119,7 +119,7 @@ bool cpu_get_bcfien(CPURISCVState *env)
}
}
-bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
+bool riscv_env_smode_dbltrp_enabled(const CPURISCVState *env, bool virt)
{
#ifdef CONFIG_USER_ONLY
return false;
@@ -163,7 +163,7 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)
* M-mode: mseccfg.PMM
* Other existing modes: disabled
*/
-RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+RISCVPmPmm riscv_pm_get_pmm(const CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
privilege_mode_t priv_mode;
@@ -215,7 +215,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
#endif
}
-RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)
+RISCVPmPmm riscv_pm_get_vm_ldst_pmm(const CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
privilege_mode_t priv_mode;
@@ -241,7 +241,7 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)
#endif
}
-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst)
+bool riscv_cpu_virt_mem_enabled(const CPURISCVState *env, bool is_vm_ldst)
{
#ifndef CONFIG_USER_ONLY
int satp_mode = 0;
@@ -426,7 +426,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
/* Return true is floating point support is currently enabled */
-bool riscv_cpu_fp_enabled(CPURISCVState *env)
+bool riscv_cpu_fp_enabled(const CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) {
@@ -439,7 +439,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
}
/* Return true is vector support is currently enabled */
-bool riscv_cpu_vector_enabled(CPURISCVState *env)
+bool riscv_cpu_vector_enabled(const CPURISCVState *env)
{
if (env->mstatus & MSTATUS_VS) {
if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) {
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 002f7e69c1f..f341865fb81 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -49,7 +49,8 @@ void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops)
/* Predicates */
#if !defined(CONFIG_USER_ONLY)
-RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit)
+RISCVException smstateen_acc_ok(const CPURISCVState *env,
+ int index, uint64_t bit)
{
bool virt = env->virt_enabled;
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 17/21] target/sparc: Constify CPUSPARCState for various cpu_*() getters
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 16/21] target/riscv: Constify CPURISCVState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-10 19:46 ` Richard Henderson
2026-09-01 9:52 ` [PATCH v5 18/21] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
` (3 subsequent siblings)
20 siblings, 1 reply; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Marc-André Lureau,
Mark Cave-Ayland, Artyom Tarasenko
Add the const qualifier to CPUSPARCState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
---
target/sparc/cpu.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5f583ed9de2..31a16c2af03 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
#endif
#if defined (TARGET_SPARC64)
-static inline int cpu_has_hypervisor(CPUSPARCState *env1)
+static inline int cpu_has_hypervisor(const CPUSPARCState *env1)
{
return env1->def.features & CPU_FEATURE_HYPV;
}
-static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
+static inline int cpu_hypervisor_mode(const CPUSPARCState *env1)
{
return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
}
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
{
return env1->pstate & PS_PRIV;
}
#else
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
{
return env1->psrs;
}
#endif
-static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
+static inline int cpu_interrupts_enabled(const CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
if (env1->psret != 0)
@@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
return 0;
}
-static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
+static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil)
{
#if !defined(TARGET_SPARC64)
/* level 15 is non-maskable on sparc v8 */
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 17/21] target/sparc: Constify CPUSPARCState for various cpu_*() getters
2026-09-01 9:52 ` [PATCH v5 17/21] target/sparc: Constify CPUSPARCState " Philippe Mathieu-Daudé
@ 2026-09-10 19:46 ` Richard Henderson
0 siblings, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:46 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, qemu-arm,
Marc-André Lureau, Mark Cave-Ayland, Artyom Tarasenko
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to CPUSPARCState when
> the argument is accessed without modification.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> Reviewed-by: Marc-André Lureau<marcandre.lureau@redhat.com>
> ---
> target/sparc/cpu.h | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v5 18/21] target/tricore: Document architectural interrupts as not implemented
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 17/21] target/sparc: Constify CPUSPARCState " Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 19/21] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
` (2 subsequent siblings)
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé
As mentioned in commit de680286b52 ("accel/tcg: Make
cpu_exec_interrupt hook mandatory"):
> Tricore doesn't currently implement the architectural
> interrupt handling.
Add a comment to help understanding why this SysemuCPUOps
has_work() handler is simply always returning %true.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 6d448727005..82b56c3cd56 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -113,6 +113,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
static bool tricore_cpu_has_work(CPUState *cs)
{
+ /* Interrupts are not implemented */
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 19/21] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart()
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 18/21] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Max Filippov
Add the const qualifier to CPUXtensaState when the
argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 442e98bd1ba..49d6ad9083d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -708,7 +708,7 @@ void xtensa_set_abi_call0(void);
bool xtensa_abi_call0(void);
#endif
-static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
+static inline uint32_t xtensa_replicate_windowstart(const CPUXtensaState *env)
{
return env->sregs[WINDOW_START] |
(env->sregs[WINDOW_START] << env->config->nareg / 4);
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 19/21] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
20 siblings, 0 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Michael Rolnik, Brian Cain,
Pierrick Bouvier, Helge Deller, Song Gao, Bibo Mao, Xianglai Li,
Laurent Vivier, Edgar E. Iglesias, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Stafford Horne,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Yoshinori Sato,
Cornelia Huck, Eric Farman, Matthew Rosato, Ilya Leoshkevich,
David Hildenbrand, Mark Cave-Ayland, Artyom Tarasenko,
Max Filippov, qemu-ppc, qemu-riscv, qemu-s390x
All functions called by target has_work() handler take a const @cpu
argument. We can now fulfill the comment added in commit c2804566f6
("target/arm: do not clear halting reason in has_work helper"),
qualifying the handler const to denote its idempotency.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/sysemu-cpu-ops.h | 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/avr/cpu.c | 3 ++-
target/hexagon/cpu.c | 4 ++--
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/loongarch/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 ++--
target/or1k/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/cpu.c | 5 ++---
target/rx/cpu.c | 2 +-
target/s390x/cpu-system.c | 4 ++--
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 4 ++--
20 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9a45596169a..095bdcd997a 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -19,10 +19,10 @@ typedef struct SysemuCPUOps {
/**
* @has_work: Callback for checking if there is work to do.
*
- * This function should be idempotent (i.e. not change state) as
+ * This function is idempotent (i.e. not change state) as
* it will likely be queried multiple times before a CPU resumes.
*/
- bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */
+ bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */
/**
* @get_memory_mapping: Callback for obtaining the memory mappings.
*/
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 7d1d036e1d3..21d4f8ac23b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool alpha_cpu_has_work(CPUState *cs)
+static bool alpha_cpu_has_work(const CPUState *cs)
{
/* Here we are checking to see if the CPU should wake up from HALT.
We will have gotten into this state only for WTINT from PALmode. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9761bb173c1..ba66359d410 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
* CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
* unconditionally.
*/
-static bool arm_cpu_has_work(CPUState *cs)
+static bool arm_cpu_has_work(const CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
+ const ARMCPU *cpu = ARM_CPU(cs);
/*
* Only another PSCI call can wake the CPU up in which case the
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a01e6fa4751..a96bef46ff1 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -23,6 +23,7 @@
#include "qemu/qemu-print.h"
#include "exec/translation-block.h"
#include "system/address-spaces.h"
+#include "hw/core/cpu.h"
#include "cpu.h"
#include "disas/dis-asm.h"
#include "tcg/debug-assert.h"
@@ -43,7 +44,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs)
return cpu->env.pc_w * 2;
}
-static bool avr_cpu_has_work(CPUState *cs)
+static bool avr_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)
&& cpu_interrupts_enabled(cpu_env(cs));
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 4cc6bd67c28..868aef0cde4 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *env)
return E_bit;
}
-static bool hexagon_cpu_has_work(CPUState *cs)
+static bool hexagon_cpu_has_work(const CPUState *cs)
{
- CPUHexagonState *env = cpu_env(cs);
+ const CPUHexagonState *env = cpu_env(cs);
return hexagon_thread_is_enabled(env) &&
(cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 7b1309a7c38..dbf58466c24 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool hppa_cpu_has_work(CPUState *cs)
+static bool hppa_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1fc02cf94e6..0606ac16664 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10638,7 +10638,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
return 0;
}
-static bool x86_cpu_has_work(CPUState *cs)
+static bool x86_cpu_has_work(const CPUState *cs)
{
return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
}
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 3b3cbde882f..3fc208e44f8 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -110,7 +110,7 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env)
#endif
#ifndef CONFIG_USER_ONLY
-static bool loongarch_cpu_has_work(CPUState *cs)
+static bool loongarch_cpu_has_work(const CPUState *cs)
{
bool has_work = false;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 523694d8fbf..da3681fab1f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool m68k_cpu_has_work(CPUState *cs)
+static bool m68k_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6013a8def8e..d1d2f0ec7e3 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool mb_cpu_has_work(CPUState *cs)
+static bool mb_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index c069aa1c0b7..0f39f8fe0a5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs)
}
#if !defined(CONFIG_USER_ONLY)
-static bool mips_cpu_has_work(CPUState *cs)
+static bool mips_cpu_has_work(const CPUState *cs)
{
- CPUMIPSState *env = cpu_env(cs);
+ const CPUMIPSState *env = cpu_env(cs);
bool has_work = false;
/*
diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
index 42d9351b6d7..10b13ae69cd 100644
--- a/target/or1k/cpu.c
+++ b/target/or1k/cpu.c
@@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool openrisc_cpu_has_work(CPUState *cs)
+static bool openrisc_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER);
}
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ef59c56f416..c72a7168a23 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7222,7 +7222,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
-static bool ppc_cpu_has_work(CPUState *cs)
+static bool ppc_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6004da4ac33..5c16c52e010 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -953,10 +953,9 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env)
(irqs | irqs_f_vs), env->hviprio);
}
-static bool riscv_cpu_has_work(CPUState *cs)
+static bool riscv_cpu_has_work(const CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
+ const CPURISCVState *env = cpu_env(cs);
/*
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 69946928995..dfa09a85bce 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs,
cpu->env.pc = data[0];
}
-static bool rx_cpu_has_work(CPUState *cs)
+static bool rx_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
}
diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c
index 84faceb3338..3a0ff46e144 100644
--- a/target/s390x/cpu-system.c
+++ b/target/s390x/cpu-system.c
@@ -39,9 +39,9 @@
#include "system/tcg.h"
#include "hw/core/sysemu-cpu-ops.h"
-static bool s390_cpu_has_work(CPUState *cs)
+static bool s390_cpu_has_work(const CPUState *cs)
{
- S390CPU *cpu = S390_CPU(cs);
+ const S390CPU *cpu = S390_CPU(cs);
/* STOPPED cpus can never wake up */
if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD &&
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 55c73a1da35..b0ed356d0f7 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
return false;
}
-static bool superh_cpu_has_work(CPUState *cs)
+static bool superh_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 2baa5036871..8dd9b0d5ee3 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool sparc_cpu_has_work(CPUState *cs)
+static bool sparc_cpu_has_work(const CPUState *cs)
{
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
cpu_interrupts_enabled(cpu_env(cs));
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 82b56c3cd56..357f3737053 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -111,7 +111,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
cpu_state_reset(cpu_env(cs));
}
-static bool tricore_cpu_has_work(CPUState *cs)
+static bool tricore_cpu_has_work(const CPUState *cs)
{
/* Interrupts are not implemented */
return true;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 99c8bd4b5fb..1b299568776 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-static bool xtensa_cpu_has_work(CPUState *cs)
+static bool xtensa_cpu_has_work(const CPUState *cs)
{
- CPUXtensaState *env = cpu_env(cs);
+ const CPUXtensaState *env = cpu_env(cs);
return !env->runstall && env->pending_irq_level;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers
2026-09-01 9:52 [PATCH v5 00/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2026-09-01 9:52 ` [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
@ 2026-09-01 9:52 ` Philippe Mathieu-Daudé
2026-09-01 11:09 ` marcandre.lureau
2026-09-10 19:49 ` Richard Henderson
20 siblings, 2 replies; 32+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-01 9:52 UTC (permalink / raw)
To: qemu-devel
Cc: Paolo Bonzini, Zhao Liu, Peter Maydell, Richard Henderson,
qemu-arm, Philippe Mathieu-Daudé, Michael Rolnik, Brian Cain,
Pierrick Bouvier, Helge Deller, Song Gao, Bibo Mao, Xianglai Li,
Laurent Vivier, Edgar E. Iglesias, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Stafford Horne,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Yoshinori Sato,
Ilya Leoshkevich, David Hildenbrand, Cornelia Huck, Eric Farman,
Matthew Rosato, Mark Cave-Ayland, Artyom Tarasenko, Max Filippov,
qemu-ppc, qemu-riscv, qemu-s390x
All functions called by cpu_mmu_index() take a const
@cpu argument. Propagate the constness to the caller
(CPU state should not mutate when resolving the MMU
index of the current translation regime).
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/accel/tcg/cpu-mmu-index.h | 2 +-
include/accel/tcg/cpu-ops.h | 2 +-
target/alpha/cpu.h | 2 +-
target/arm/internals.h | 4 ++--
target/i386/tcg/tcg-cpu.h | 2 +-
target/ppc/cpu.h | 2 +-
target/s390x/cpu.h | 2 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/hexagon/cpu.c | 6 +++---
target/hppa/cpu.c | 4 ++--
target/i386/tcg/tcg-cpu.c | 6 +++---
target/loongarch/tcg/tcg_cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 6 +++---
target/mips/cpu.c | 2 +-
target/or1k/cpu.c | 4 ++--
target/ppc/cpu_init.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 4 ++--
target/sparc/cpu.c | 4 ++--
target/tricore/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
26 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h
index e0fb6ef91c8..01152075372 100644
--- a/include/accel/tcg/cpu-mmu-index.h
+++ b/include/accel/tcg/cpu-mmu-index.h
@@ -30,7 +30,7 @@
* Return the core mmu index for the current translation regime.
* This function is used by generic TCG code paths.
*/
-static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
+static inline int cpu_mmu_index(const CPUState *cs, bool ifetch)
{
#ifdef COMPILING_PER_TARGET
# ifdef CONFIG_USER_ONLY
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index a88cc4dc572..69d7ec29115 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -102,7 +102,7 @@ struct TCGCPUOps {
void (*debug_excp_handler)(CPUState *cpu);
/** @mmu_index: Callback for choosing softmmu mmu index */
- int (*mmu_index)(CPUState *cpu, bool ifetch);
+ int (*mmu_index)(const CPUState *cpu, bool ifetch);
#ifdef CONFIG_USER_ONLY
/**
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 378bd96d941..1c9f9fce20b 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -383,7 +383,7 @@ enum {
#define TB_FLAG_UNALIGN (1u << 1)
-static inline int alpha_env_mmu_index(CPUAlphaState *env)
+static inline int alpha_env_mmu_index(const CPUAlphaState *env)
{
int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
if (env->flags & ENV_FLAG_PAL_MODE) {
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f1a80c890ee..d582cefcfa4 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -55,7 +55,7 @@ static inline MemOp mo_endian(const CPUARMState *env)
return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE;
}
-static inline int arm_env_mmu_index(CPUARMState *env)
+static inline int arm_env_mmu_index(const CPUARMState *env)
{
return EX_TBFLAG_ANY(env->hflags, MMUIDX);
}
@@ -431,7 +431,7 @@ void arm_restore_state_to_opc(CPUState *cs,
#ifdef CONFIG_TCG
TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs);
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-int arm_cpu_mmu_index(CPUState *cs, bool ifetch);
+int arm_cpu_mmu_index(const CPUState *cs, bool ifetch);
#endif /* CONFIG_TCG */
typedef enum ARMFPRounding {
diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
index 85bcd61678f..1127861e337 100644
--- a/target/i386/tcg/tcg-cpu.h
+++ b/target/i386/tcg/tcg-cpu.h
@@ -82,6 +82,6 @@ extern const TCGCPUOps x86_tcg_ops;
bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
-int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
+int x86_mmu_index_pl(const CPUX86State *env, unsigned pl);
#endif /* TCG_CPU_H */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3fb51bbeb82..56264752c1b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1736,7 +1736,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
/* MMU modes definitions */
#define MMU_USER_IDX 0
-static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
+static inline int ppc_env_mmu_index(const CPUPPCState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 998bbb0d7ff..cd5f9256b24 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -373,7 +373,7 @@ QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT);
#define MMU_HOME_IDX 2
#define MMU_REAL_IDX 3
-static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
+static inline int s390x_env_mmu_index(const CPUS390XState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 21d4f8ac23b..3bf88702dc1 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -93,7 +93,7 @@ static bool alpha_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int alpha_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return alpha_env_mmu_index(cpu_env(cs));
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ba66359d410..63ef00735ca 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -126,7 +126,7 @@ void arm_restore_state_to_opc(CPUState *cs,
}
}
-int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
+int arm_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return arm_env_mmu_index(cpu_env(cs));
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a96bef46ff1..24a5a9debc9 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -50,7 +50,7 @@ static bool avr_cpu_has_work(const CPUState *cs)
&& cpu_interrupts_enabled(cpu_env(cs));
}
-static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int avr_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 868aef0cde4..2bc58fc6305 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -482,11 +482,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
mcc->parent_realize(dev, errp);
}
-static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int hexagon_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
#ifndef CONFIG_USER_ONLY
- CPUHexagonState *env = cpu_env(cs);
- HexagonCPU *cpu = HEXAGON_CPU(cs);
+ const CPUHexagonState *env = cpu_env(cs);
+ const HexagonCPU *cpu = HEXAGON_CPU(cs);
int cpu_mode;
BQL_LOCK_GUARD();
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index dbf58466c24..ec351302406 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -140,9 +140,9 @@ static bool hppa_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int hppa_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUHPPAState *env = cpu_env(cs);
+ const CPUHPPAState *env = cpu_env(cs);
if (env->psw & (ifetch ? PSW_C : PSW_D)) {
return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index e4fc212aca5..da1498ee45d 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -114,7 +114,7 @@ static void x86_restore_state_to_opc(CPUState *cs,
}
}
-int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
+int x86_mmu_index_pl(const CPUX86State *env, unsigned pl)
{
int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1;
int mmu_index_base =
@@ -125,9 +125,9 @@ int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
return mmu_index_base + mmu_index_32;
}
-static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int x86_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUX86State *env = cpu_env(cs);
+ const CPUX86State *env = cpu_env(cs);
return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK);
}
diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
index 7ea2a1eb933..a26233d5eed 100644
--- a/target/loongarch/tcg/tcg_cpu.c
+++ b/target/loongarch/tcg/tcg_cpu.c
@@ -301,9 +301,9 @@ static void loongarch_restore_state_to_opc(CPUState *cs,
set_pc(cpu_env(cs), data[0]);
}
-static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int loongarch_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPULoongArchState *env = cpu_env(cs);
+ const CPULoongArchState *env = cpu_env(cs);
CPUSysState *sys = env_sys(env);
if (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG)) {
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index da3681fab1f..f1fd2e6f14d 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -82,7 +82,7 @@ static bool m68k_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int m68k_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX;
}
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index d1d2f0ec7e3..524175d2236 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -133,10 +133,10 @@ static bool mb_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int mb_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUMBState *env = cpu_env(cs);
- MicroBlazeCPU *cpu = env_archcpu(env);
+ const CPUMBState *env = cpu_env(cs);
+ const MicroBlazeCPU *cpu = env_archcpu(env);
/* Are we in nommu mode?. */
if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0f39f8fe0a5..a428176d9e8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -671,7 +671,7 @@ static const Property mips_cpu_properties[] = {
#ifdef CONFIG_TCG
#include "accel/tcg/cpu-ops.h"
-static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
+static int mips_cpu_mmu_index(const CPUState *cs, bool ifunc)
{
return mips_env_mmu_index(cpu_env(cs));
}
diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
index 10b13ae69cd..c9ab5c0f1c1 100644
--- a/target/or1k/cpu.c
+++ b/target/or1k/cpu.c
@@ -82,9 +82,9 @@ static bool openrisc_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int openrisc_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUOpenRISCState *env = cpu_env(cs);
+ const CPUOpenRISCState *env = cpu_env(cs);
if (env->sr & (ifetch ? SR_IME : SR_DME)) {
/* The mmu is enabled; test supervisor state. */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c72a7168a23..a33a074b796 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7215,7 +7215,7 @@ static void ppc_restore_state_to_opc(CPUState *cs,
cpu->env.nip = data[0];
}
-static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int ppc_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return ppc_env_mmu_index(cpu_env(cs), ifetch);
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index cd303660f1f..a0210ca50e3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -95,7 +95,7 @@ static const char *cpu_priv_ver_to_str(int priv_ver)
return priv_spec_str;
}
-static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int riscv_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return riscv_env_mmu_index(cpu_env(cs), ifetch);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index dfa09a85bce..c5dfba8976a 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -78,7 +78,7 @@ static bool rx_cpu_has_work(const CPUState *cs)
return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
}
-static int rx_cpu_mmu_index(CPUState *cs, bool ifunc)
+static int rx_cpu_mmu_index(const CPUState *cs, bool ifunc)
{
return 0;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index c34f4b23472..a043f1e7920 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -311,7 +311,7 @@ static const Property s390x_cpu_properties[] = {
#include "accel/tcg/cpu-ops.h"
#include "tcg/tcg_s390x.h"
-static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int s390x_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return s390x_env_mmu_index(cpu_env(cs), ifetch);
}
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index b0ed356d0f7..f8b33844d2a 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -113,9 +113,9 @@ static bool superh_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int sh4_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUSH4State *env = cpu_env(cs);
+ const CPUSH4State *env = cpu_env(cs);
/*
* The instruction in a RTE delay slot is fetched in privileged mode,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8dd9b0d5ee3..f1ae16c91e9 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -790,9 +790,9 @@ static bool sparc_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int sparc_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
- CPUSPARCState *env = cpu_env(cs);
+ const CPUSPARCState *env = cpu_env(cs);
#ifndef TARGET_SPARC64
if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 357f3737053..09d4270df60 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -117,7 +117,7 @@ static bool tricore_cpu_has_work(const CPUState *cs)
return true;
}
-static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int tricore_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return 0;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 1b299568776..8cf973632e7 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -148,7 +148,7 @@ static bool xtensa_cpu_has_work(const CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch)
+static int xtensa_cpu_mmu_index(const CPUState *cs, bool ifetch)
{
return xtensa_get_cring(cpu_env(cs));
}
--
2.53.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
@ 2026-09-01 11:09 ` marcandre.lureau
2026-09-10 19:49 ` Richard Henderson
1 sibling, 0 replies; 32+ messages in thread
From: marcandre.lureau @ 2026-09-01 11:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Paolo Bonzini, Zhao Liu, Peter Maydell,
Richard Henderson, qemu-arm, Michael Rolnik, Brian Cain,
Pierrick Bouvier, Helge Deller, Song Gao, Bibo Mao, Xianglai Li,
Laurent Vivier, Edgar E. Iglesias, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, Stafford Horne,
Chinmay Rath, Nicholas Piggin, Glenn Miles, Harsh Prateek Bora,
Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Chao Liu, Yoshinori Sato,
Ilya Leoshkevich, David Hildenbrand, Cornelia Huck, Eric Farman,
Matthew Rosato, Mark Cave-Ayland, Artyom Tarasenko, Max Filippov,
qemu-ppc, qemu-riscv, qemu-s390x
On 2026-09-01 11:52 +0200, Philippe Mathieu-Daudé wrote:
> All functions called by cpu_mmu_index() take a const
> @cpu argument. Propagate the constness to the caller
> (CPU state should not mutate when resolving the MMU
> index of the current translation regime).
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
> ---
> include/accel/tcg/cpu-mmu-index.h | 2 +-
> include/accel/tcg/cpu-ops.h | 2 +-
> target/alpha/cpu.h | 2 +-
> target/arm/internals.h | 4 ++--
> target/i386/tcg/tcg-cpu.h | 2 +-
> target/ppc/cpu.h | 2 +-
> target/s390x/cpu.h | 2 +-
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/hexagon/cpu.c | 6 +++---
> target/hppa/cpu.c | 4 ++--
> target/i386/tcg/tcg-cpu.c | 6 +++---
> target/loongarch/tcg/tcg_cpu.c | 4 ++--
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 6 +++---
> target/mips/cpu.c | 2 +-
> target/or1k/cpu.c | 4 ++--
> target/ppc/cpu_init.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 4 ++--
> target/sparc/cpu.c | 4 ++--
> target/tricore/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 26 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h
> index e0fb6ef91c8..01152075372 100644
> --- a/include/accel/tcg/cpu-mmu-index.h
> +++ b/include/accel/tcg/cpu-mmu-index.h
> @@ -30,7 +30,7 @@
> * Return the core mmu index for the current translation regime.
> * This function is used by generic TCG code paths.
> */
> -static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
> +static inline int cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> #ifdef COMPILING_PER_TARGET
> # ifdef CONFIG_USER_ONLY
> diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
> index a88cc4dc572..69d7ec29115 100644
> --- a/include/accel/tcg/cpu-ops.h
> +++ b/include/accel/tcg/cpu-ops.h
> @@ -102,7 +102,7 @@ struct TCGCPUOps {
> void (*debug_excp_handler)(CPUState *cpu);
>
> /** @mmu_index: Callback for choosing softmmu mmu index */
> - int (*mmu_index)(CPUState *cpu, bool ifetch);
> + int (*mmu_index)(const CPUState *cpu, bool ifetch);
>
> #ifdef CONFIG_USER_ONLY
> /**
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index 378bd96d941..1c9f9fce20b 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -383,7 +383,7 @@ enum {
>
> #define TB_FLAG_UNALIGN (1u << 1)
>
> -static inline int alpha_env_mmu_index(CPUAlphaState *env)
> +static inline int alpha_env_mmu_index(const CPUAlphaState *env)
> {
> int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
> if (env->flags & ENV_FLAG_PAL_MODE) {
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index f1a80c890ee..d582cefcfa4 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -55,7 +55,7 @@ static inline MemOp mo_endian(const CPUARMState *env)
> return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE;
> }
>
> -static inline int arm_env_mmu_index(CPUARMState *env)
> +static inline int arm_env_mmu_index(const CPUARMState *env)
> {
> return EX_TBFLAG_ANY(env->hflags, MMUIDX);
> }
> @@ -431,7 +431,7 @@ void arm_restore_state_to_opc(CPUState *cs,
> #ifdef CONFIG_TCG
> TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs);
> void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
> -int arm_cpu_mmu_index(CPUState *cs, bool ifetch);
> +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch);
> #endif /* CONFIG_TCG */
>
> typedef enum ARMFPRounding {
> diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
> index 85bcd61678f..1127861e337 100644
> --- a/target/i386/tcg/tcg-cpu.h
> +++ b/target/i386/tcg/tcg-cpu.h
> @@ -82,6 +82,6 @@ extern const TCGCPUOps x86_tcg_ops;
>
> bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
>
> -int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
> +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl);
>
> #endif /* TCG_CPU_H */
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 3fb51bbeb82..56264752c1b 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1736,7 +1736,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
>
> /* MMU modes definitions */
> #define MMU_USER_IDX 0
> -static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
> +static inline int ppc_env_mmu_index(const CPUPPCState *env, bool ifetch)
> {
> #ifdef CONFIG_USER_ONLY
> return MMU_USER_IDX;
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 998bbb0d7ff..cd5f9256b24 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -373,7 +373,7 @@ QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT);
> #define MMU_HOME_IDX 2
> #define MMU_REAL_IDX 3
>
> -static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
> +static inline int s390x_env_mmu_index(const CPUS390XState *env, bool ifetch)
> {
> #ifdef CONFIG_USER_ONLY
> return MMU_USER_IDX;
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index 21d4f8ac23b..3bf88702dc1 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -93,7 +93,7 @@ static bool alpha_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int alpha_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return alpha_env_mmu_index(cpu_env(cs));
> }
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index ba66359d410..63ef00735ca 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -126,7 +126,7 @@ void arm_restore_state_to_opc(CPUState *cs,
> }
> }
>
> -int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
> +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return arm_env_mmu_index(cpu_env(cs));
> }
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index a96bef46ff1..24a5a9debc9 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -50,7 +50,7 @@ static bool avr_cpu_has_work(const CPUState *cs)
> && cpu_interrupts_enabled(cpu_env(cs));
> }
>
> -static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int avr_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
> }
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 868aef0cde4..2bc58fc6305 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -482,11 +482,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
> mcc->parent_realize(dev, errp);
> }
>
> -static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int hexagon_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> #ifndef CONFIG_USER_ONLY
> - CPUHexagonState *env = cpu_env(cs);
> - HexagonCPU *cpu = HEXAGON_CPU(cs);
> + const CPUHexagonState *env = cpu_env(cs);
> + const HexagonCPU *cpu = HEXAGON_CPU(cs);
> int cpu_mode;
>
> BQL_LOCK_GUARD();
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index dbf58466c24..ec351302406 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -140,9 +140,9 @@ static bool hppa_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int hppa_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUHPPAState *env = cpu_env(cs);
> + const CPUHPPAState *env = cpu_env(cs);
>
> if (env->psw & (ifetch ? PSW_C : PSW_D)) {
> return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
> diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
> index e4fc212aca5..da1498ee45d 100644
> --- a/target/i386/tcg/tcg-cpu.c
> +++ b/target/i386/tcg/tcg-cpu.c
> @@ -114,7 +114,7 @@ static void x86_restore_state_to_opc(CPUState *cs,
> }
> }
>
> -int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
> +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl)
> {
> int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1;
> int mmu_index_base =
> @@ -125,9 +125,9 @@ int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
> return mmu_index_base + mmu_index_32;
> }
>
> -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int x86_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUX86State *env = cpu_env(cs);
> + const CPUX86State *env = cpu_env(cs);
> return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK);
> }
>
> diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c
> index 7ea2a1eb933..a26233d5eed 100644
> --- a/target/loongarch/tcg/tcg_cpu.c
> +++ b/target/loongarch/tcg/tcg_cpu.c
> @@ -301,9 +301,9 @@ static void loongarch_restore_state_to_opc(CPUState *cs,
> set_pc(cpu_env(cs), data[0]);
> }
>
> -static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int loongarch_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPULoongArchState *env = cpu_env(cs);
> + const CPULoongArchState *env = cpu_env(cs);
> CPUSysState *sys = env_sys(env);
>
> if (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG)) {
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index da3681fab1f..f1fd2e6f14d 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -82,7 +82,7 @@ static bool m68k_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int m68k_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX;
> }
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index d1d2f0ec7e3..524175d2236 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -133,10 +133,10 @@ static bool mb_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int mb_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUMBState *env = cpu_env(cs);
> - MicroBlazeCPU *cpu = env_archcpu(env);
> + const CPUMBState *env = cpu_env(cs);
> + const MicroBlazeCPU *cpu = env_archcpu(env);
>
> /* Are we in nommu mode?. */
> if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 0f39f8fe0a5..a428176d9e8 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -671,7 +671,7 @@ static const Property mips_cpu_properties[] = {
> #ifdef CONFIG_TCG
> #include "accel/tcg/cpu-ops.h"
>
> -static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
> +static int mips_cpu_mmu_index(const CPUState *cs, bool ifunc)
> {
> return mips_env_mmu_index(cpu_env(cs));
> }
> diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
> index 10b13ae69cd..c9ab5c0f1c1 100644
> --- a/target/or1k/cpu.c
> +++ b/target/or1k/cpu.c
> @@ -82,9 +82,9 @@ static bool openrisc_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int openrisc_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUOpenRISCState *env = cpu_env(cs);
> + const CPUOpenRISCState *env = cpu_env(cs);
>
> if (env->sr & (ifetch ? SR_IME : SR_DME)) {
> /* The mmu is enabled; test supervisor state. */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index c72a7168a23..a33a074b796 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7215,7 +7215,7 @@ static void ppc_restore_state_to_opc(CPUState *cs,
> cpu->env.nip = data[0];
> }
>
> -static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int ppc_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return ppc_env_mmu_index(cpu_env(cs), ifetch);
> }
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index cd303660f1f..a0210ca50e3 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -95,7 +95,7 @@ static const char *cpu_priv_ver_to_str(int priv_ver)
> return priv_spec_str;
> }
>
> -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int riscv_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return riscv_env_mmu_index(cpu_env(cs), ifetch);
> }
> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
> index dfa09a85bce..c5dfba8976a 100644
> --- a/target/rx/cpu.c
> +++ b/target/rx/cpu.c
> @@ -78,7 +78,7 @@ static bool rx_cpu_has_work(const CPUState *cs)
> return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
> }
>
> -static int rx_cpu_mmu_index(CPUState *cs, bool ifunc)
> +static int rx_cpu_mmu_index(const CPUState *cs, bool ifunc)
> {
> return 0;
> }
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index c34f4b23472..a043f1e7920 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -311,7 +311,7 @@ static const Property s390x_cpu_properties[] = {
> #include "accel/tcg/cpu-ops.h"
> #include "tcg/tcg_s390x.h"
>
> -static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int s390x_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return s390x_env_mmu_index(cpu_env(cs), ifetch);
> }
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index b0ed356d0f7..f8b33844d2a 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -113,9 +113,9 @@ static bool superh_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int sh4_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUSH4State *env = cpu_env(cs);
> + const CPUSH4State *env = cpu_env(cs);
>
> /*
> * The instruction in a RTE delay slot is fetched in privileged mode,
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 8dd9b0d5ee3..f1ae16c91e9 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -790,9 +790,9 @@ static bool sparc_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int sparc_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> - CPUSPARCState *env = cpu_env(cs);
> + const CPUSPARCState *env = cpu_env(cs);
>
> #ifndef TARGET_SPARC64
> if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index 357f3737053..09d4270df60 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -117,7 +117,7 @@ static bool tricore_cpu_has_work(const CPUState *cs)
> return true;
> }
>
> -static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int tricore_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return 0;
> }
> diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
> index 1b299568776..8cf973632e7 100644
> --- a/target/xtensa/cpu.c
> +++ b/target/xtensa/cpu.c
> @@ -148,7 +148,7 @@ static bool xtensa_cpu_has_work(const CPUState *cs)
> }
> #endif /* !CONFIG_USER_ONLY */
>
> -static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch)
> +static int xtensa_cpu_mmu_index(const CPUState *cs, bool ifetch)
> {
> return xtensa_get_cring(cpu_env(cs));
> }
> --
> 2.53.0
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers
2026-09-01 9:52 ` [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Philippe Mathieu-Daudé
2026-09-01 11:09 ` marcandre.lureau
@ 2026-09-10 19:49 ` Richard Henderson
1 sibling, 0 replies; 32+ messages in thread
From: Richard Henderson @ 2026-09-10 19:49 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 8/31/26 23:52, Philippe Mathieu-Daudé wrote:
> All functions called by cpu_mmu_index() take a const
> @cpu argument. Propagate the constness to the caller
> (CPU state should not mutate when resolving the MMU
> index of the current translation regime).
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> ---
> include/accel/tcg/cpu-mmu-index.h | 2 +-
> include/accel/tcg/cpu-ops.h | 2 +-
> target/alpha/cpu.h | 2 +-
> target/arm/internals.h | 4 ++--
> target/i386/tcg/tcg-cpu.h | 2 +-
> target/ppc/cpu.h | 2 +-
> target/s390x/cpu.h | 2 +-
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/hexagon/cpu.c | 6 +++---
> target/hppa/cpu.c | 4 ++--
> target/i386/tcg/tcg-cpu.c | 6 +++---
> target/loongarch/tcg/tcg_cpu.c | 4 ++--
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 6 +++---
> target/mips/cpu.c | 2 +-
> target/or1k/cpu.c | 4 ++--
> target/ppc/cpu_init.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 4 ++--
> target/sparc/cpu.c | 4 ++--
> target/tricore/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 26 files changed, 38 insertions(+), 38 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
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