From: Bin Meng <bin.meng@processmission.com>
To: QEMU <qemu-devel@nongnu.org>
Cc: Conor Dooley <conor@kernel.org>, Fabiano Rosas <farosas@suse.de>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sebastian Huber <sebastian.huber@embedded-brains.de>,
qemu-riscv@nongnu.org
Subject: [PATCH v2 15/24] tests/qtest: Add PolarFire SoC RTC coverage
Date: Fri, 4 Sep 2026 23:57:34 +0800 [thread overview]
Message-ID: <20260904155758.3833179-16-bin.meng@processmission.com> (raw)
In-Reply-To: <20260904155758.3833179-1-bin.meng@processmission.com>
Exercise RTC register masks, binary counter, upload and stop controls,
alarm and wakeup interrupt behavior, reset state, and PLIC wiring on
the Icicle Kit.
Also verify RTC state and pending interrupt migration, including streams
from QEMU versions that predate the RTC device.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
---
Changes in v2:
- Expect the documented hardware state after RTC reset
MAINTAINERS | 1 +
tests/qtest/mchp_pfsoc_rtc_test.c | 315 ++++++++++++++++++++++++++++++
tests/qtest/meson.build | 5 +-
3 files changed, 320 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/mchp_pfsoc_rtc_test.c
diff --git a/MAINTAINERS b/MAINTAINERS
index adc4a41266..1856c67feb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1806,6 +1806,7 @@ F: include/hw/misc/mchp_pfsoc_l2cc.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
F: include/hw/rtc/mchp_pfsoc_rtc.h
F: tests/qtest/mchp_pfsoc_l2cc_test.c
+F: tests/qtest/mchp_pfsoc_rtc_test.c
Shakti C class SoC
L: qemu-riscv@nongnu.org
diff --git a/tests/qtest/mchp_pfsoc_rtc_test.c b/tests/qtest/mchp_pfsoc_rtc_test.c
new file mode 100644
index 0000000000..ed96c15faa
--- /dev/null
+++ b/tests/qtest/mchp_pfsoc_rtc_test.c
@@ -0,0 +1,315 @@
+/*
+ * QTest testcase for the Microchip PolarFire SoC RTC
+ *
+ * Copyright (c) 2026 Process Mission
+ *
+ * Author:
+ * Bin Meng <bin.meng@processmission.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/bswap.h"
+#include "qemu/timer.h"
+#include "libqtest.h"
+#include "migration/migration-qmp.h"
+#include "migration/migration-util.h"
+
+#define RTC_BASE 0x20124000
+#define RTC_CONTROL 0x00
+#define RTC_MODE 0x04
+#define RTC_PRESCALER 0x08
+#define RTC_ALARM_LOWER 0x0c
+#define RTC_ALARM_UPPER 0x10
+#define RTC_COMPARE_LOWER 0x14
+#define RTC_COMPARE_UPPER 0x18
+#define RTC_DATETIME_LOWER 0x20
+#define RTC_DATETIME_UPPER 0x24
+#define RTC_RUNNING BIT(0)
+#define RTC_STOP BIT(1)
+#define RTC_ALARM_ON BIT(2)
+#define RTC_ALARM_OFF BIT(3)
+#define RTC_UPLOAD BIT(5)
+#define RTC_MATCH BIT(7)
+#define RTC_WAKEUP_CLEAR BIT(8)
+#define RTC_WAKEUP_SET BIT(9)
+#define RTC_UPDATED BIT(10)
+#define RTC_WAKEUP_ENABLE BIT(1)
+#define RTC_WAKEUP_RESET BIT(2)
+#define RTC_WAKEUP_CONTINUE BIT(3)
+#define RTC_PRESCALER_MASK 0x03ffffff
+#define RTC_UPPER_MASK 0x3fffffff
+#define PLIC_BASE 0x0c000000
+#define PLIC_PENDING 0x1000
+#define PLIC_RTC_PENDING (BIT(16) | BIT(17))
+#define ENVM_BASE 0x20220000
+#define HSS_HEADER_SIZE 0x100
+#define HSS_HEADER_JUMP 0x1000006f
+#define HSS_PAYLOAD_BASE (ENVM_BASE + HSS_HEADER_SIZE)
+#define HSS_PAYLOAD_SIZE 8
+
+static QTestState *microchip_icicle_kit_start_rtc(const char *firmware)
+{
+ return qtest_initf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G -bios \"%s\" "
+ "-rtc clock=vm", firmware);
+}
+
+static QTestState *microchip_icicle_kit_start_ext(const char *qemu_var,
+ const char *firmware)
+{
+ g_autofree char *args = g_strdup_printf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G -bios \"%s\"",
+ firmware);
+
+ return qtest_init_ext(qemu_var, args, NULL, true);
+}
+
+static char *create_firmware(void)
+{
+ uint8_t firmware[HSS_HEADER_SIZE + HSS_PAYLOAD_SIZE] = { 0 };
+ static const uint8_t payload[] = {
+ 0x13, 0x00, 0x00, 0x00,
+ 0x6f, 0x00, 0x00, 0x00,
+ };
+ char *path;
+ int fd;
+ ssize_t written;
+ unsigned int i;
+
+ stl_le_p(&firmware[0], HSS_HEADER_JUMP);
+ stl_le_p(&firmware[4], HSS_PAYLOAD_SIZE);
+ for (i = 0; i < 5; i++) {
+ stl_le_p(&firmware[8 + i * sizeof(uint32_t)], HSS_PAYLOAD_BASE);
+ }
+ memcpy(&firmware[HSS_HEADER_SIZE], payload, sizeof(payload));
+
+ fd = g_file_open_tmp("microchip-icicle-kit-XXXXXX", &path, NULL);
+ g_assert_cmpint(fd, >=, 0);
+
+ written = write(fd, firmware, sizeof(firmware));
+ g_assert_cmpint(written, ==, sizeof(firmware));
+ close(fd);
+
+ return path;
+}
+
+static uint64_t rtc_read_binary_count(QTestState *qts)
+{
+ uint64_t count = qtest_readl(qts, RTC_BASE + RTC_DATETIME_LOWER);
+
+ count |= (uint64_t)qtest_readl(qts,
+ RTC_BASE + RTC_DATETIME_UPPER) << 32;
+ return count;
+}
+
+static void test_rtc(void)
+{
+ g_autofree char *firmware = create_firmware();
+ QTestState *qts = microchip_icicle_kit_start_rtc(firmware);
+ uint32_t control;
+
+ unlink(firmware);
+ qtest_irq_intercept_out_named(qts, "/machine/soc/rtc", "sysbus-irq");
+
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL), ==, 0);
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 0);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 0);
+
+ qtest_writel(qts, RTC_BASE + RTC_MODE, UINT32_MAX);
+ qtest_writel(qts, RTC_BASE + RTC_PRESCALER, UINT32_MAX);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_MODE), ==, 0xf);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_PRESCALER), ==,
+ RTC_PRESCALER_MASK);
+ qtest_writel(qts, RTC_BASE + RTC_MODE, 0);
+
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_STOP);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL) &
+ RTC_RUNNING, ==, 0);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 0);
+
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_LOWER, 42);
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_UPPER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_UPLOAD);
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 42);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL) &
+ (RTC_UPLOAD | RTC_UPDATED), ==, RTC_UPDATED);
+
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_RUNNING);
+ qtest_clock_step(qts, NANOSECONDS_PER_SECOND);
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 43);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_WAKEUP_SET);
+ g_assert_true(qtest_get_irq(qts, 0));
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_WAKEUP_CLEAR);
+ g_assert_false(qtest_get_irq(qts, 0));
+
+ qtest_writel(qts, RTC_BASE + RTC_ALARM_LOWER, 45);
+ qtest_writel(qts, RTC_BASE + RTC_ALARM_UPPER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_COMPARE_LOWER, UINT32_MAX);
+ qtest_writel(qts, RTC_BASE + RTC_COMPARE_UPPER, RTC_UPPER_MASK);
+ qtest_writel(qts, RTC_BASE + RTC_MODE,
+ RTC_WAKEUP_ENABLE | RTC_WAKEUP_CONTINUE);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_ON);
+ g_assert_false(qtest_get_irq(qts, 0));
+ g_assert_false(qtest_get_irq(qts, 1));
+ control = qtest_readl(qts, RTC_BASE + RTC_CONTROL);
+ g_assert_cmphex(control & RTC_ALARM_ON, ==, RTC_ALARM_ON);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, control | RTC_ALARM_OFF);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL) &
+ RTC_ALARM_ON, ==, 0);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_false(qtest_get_irq(qts, 0));
+ g_assert_false(qtest_get_irq(qts, 1));
+
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_LOWER, 43);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_UPLOAD);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_ON);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_true(qtest_get_irq(qts, 0));
+ g_assert_true(qtest_get_irq(qts, 1));
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL) & RTC_MATCH,
+ ==, RTC_MATCH);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_OFF);
+ g_assert_false(qtest_get_irq(qts, 0));
+ g_assert_false(qtest_get_irq(qts, 1));
+
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_LOWER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_UPPER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_UPLOAD);
+ qtest_writel(qts, RTC_BASE + RTC_ALARM_LOWER, 2);
+ qtest_writel(qts, RTC_BASE + RTC_MODE,
+ RTC_WAKEUP_ENABLE | RTC_WAKEUP_RESET |
+ RTC_WAKEUP_CONTINUE);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_ON);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_true(qtest_get_irq(qts, 0));
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL) &
+ RTC_ALARM_ON, ==, RTC_ALARM_ON);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_WAKEUP_CLEAR);
+ qtest_clock_step(qts, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_true(qtest_get_irq(qts, 0));
+ g_assert_cmphex(rtc_read_binary_count(qts), ==, 0);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_OFF);
+ g_assert_false(qtest_get_irq(qts, 0));
+ g_assert_false(qtest_get_irq(qts, 1));
+
+ qtest_system_reset(qts);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_CONTROL), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_MODE), ==, 0);
+ g_assert_cmphex(qtest_readl(qts, RTC_BASE + RTC_PRESCALER), ==, 0);
+ g_assert_false(qtest_get_irq(qts, 0));
+ g_assert_false(qtest_get_irq(qts, 1));
+
+ qtest_quit(qts);
+}
+
+static void test_rtc_plic(void)
+{
+ g_autofree char *firmware = create_firmware();
+ QTestState *qts = microchip_icicle_kit_start_rtc(firmware);
+
+ unlink(firmware);
+
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_LOWER, 42);
+ qtest_writel(qts, RTC_BASE + RTC_DATETIME_UPPER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_UPLOAD);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_RUNNING);
+ qtest_writel(qts, RTC_BASE + RTC_ALARM_LOWER, 43);
+ qtest_writel(qts, RTC_BASE + RTC_ALARM_UPPER, 0);
+ qtest_writel(qts, RTC_BASE + RTC_COMPARE_LOWER, UINT32_MAX);
+ qtest_writel(qts, RTC_BASE + RTC_COMPARE_UPPER, RTC_UPPER_MASK);
+ qtest_writel(qts, RTC_BASE + RTC_MODE,
+ RTC_WAKEUP_ENABLE | RTC_WAKEUP_CONTINUE);
+ qtest_writel(qts, RTC_BASE + RTC_CONTROL, RTC_ALARM_ON);
+ qtest_clock_step(qts, NANOSECONDS_PER_SECOND);
+
+ g_assert_cmphex(qtest_readl(qts, PLIC_BASE + PLIC_PENDING + 8) &
+ PLIC_RTC_PENDING, ==, PLIC_RTC_PENDING);
+
+ qtest_quit(qts);
+}
+
+static void test_machine_migration(void)
+{
+ g_autofree char *firmware = create_firmware();
+ const char *old_qemu = g_getenv("QTEST_QEMU_BINARY_OLD");
+ QTestState *from;
+ QTestState *to = qtest_initf(
+ "-machine microchip-icicle-kit -smp 5 -m 2G "
+ "-bios \"%s\" -incoming defer "
+ "-rtc clock=vm", firmware);
+
+ qtest_irq_intercept_out_named(to, "/machine/soc/rtc", "sysbus-irq");
+
+ /* Allow an older QEMU source to exercise migration compatibility */
+ if (old_qemu) {
+ from = microchip_icicle_kit_start_ext("QTEST_QEMU_BINARY_OLD",
+ firmware);
+ } else {
+ from = microchip_icicle_kit_start_rtc(firmware);
+ qtest_writel(from, RTC_BASE + RTC_DATETIME_LOWER, 0x23456789);
+ qtest_writel(from, RTC_BASE + RTC_DATETIME_UPPER, 1);
+ qtest_writel(from, RTC_BASE + RTC_CONTROL, RTC_UPLOAD);
+ qtest_writel(from, RTC_BASE + RTC_CONTROL, RTC_RUNNING);
+ qtest_writel(from, RTC_BASE + RTC_ALARM_LOWER, 0x2345678b);
+ qtest_writel(from, RTC_BASE + RTC_ALARM_UPPER, 1);
+ qtest_writel(from, RTC_BASE + RTC_COMPARE_LOWER, UINT32_MAX);
+ qtest_writel(from, RTC_BASE + RTC_COMPARE_UPPER, RTC_UPPER_MASK);
+ qtest_writel(from, RTC_BASE + RTC_MODE,
+ RTC_WAKEUP_ENABLE | RTC_WAKEUP_CONTINUE);
+ qtest_writel(from, RTC_BASE + RTC_CONTROL, RTC_ALARM_ON);
+ qtest_writel(from, RTC_BASE + RTC_CONTROL, RTC_WAKEUP_SET);
+ qtest_writel(from, RTC_BASE + RTC_PRESCALER, 999999);
+ }
+
+ unlink(firmware);
+
+ migrate_incoming_qmp(to, "tcp:127.0.0.1:0", NULL, "{}");
+ migrate_qmp(from, to, NULL, NULL, "{}");
+ wait_for_migration_complete(from);
+
+ if (old_qemu) {
+ g_assert_cmphex(qtest_readl(to, RTC_BASE + RTC_CONTROL), ==, 0);
+ g_assert_cmphex(qtest_readl(to, RTC_BASE + RTC_PRESCALER), ==, 0);
+ g_assert_false(qtest_get_irq(to, 0));
+ g_assert_false(qtest_get_irq(to, 1));
+ } else {
+ g_assert_cmphex(rtc_read_binary_count(to), ==, 0x123456789);
+ g_assert_cmphex(qtest_readl(to, RTC_BASE + RTC_CONTROL) &
+ (RTC_RUNNING | RTC_ALARM_ON), ==,
+ RTC_RUNNING | RTC_ALARM_ON);
+ g_assert_cmphex(qtest_readl(to, RTC_BASE + RTC_PRESCALER), ==,
+ 999999);
+ g_assert_true(qtest_get_irq(to, 0));
+ g_assert_false(qtest_get_irq(to, 1));
+ qtest_writel(to, RTC_BASE + RTC_CONTROL, RTC_WAKEUP_CLEAR);
+ g_assert_false(qtest_get_irq(to, 0));
+ qtest_clock_step(to, 2 * NANOSECONDS_PER_SECOND);
+ g_assert_cmphex(rtc_read_binary_count(to), ==, 0x12345678b);
+ g_assert_true(qtest_get_irq(to, 0));
+ g_assert_true(qtest_get_irq(to, 1));
+ qtest_writel(to, RTC_BASE + RTC_CONTROL, RTC_ALARM_OFF);
+ g_assert_false(qtest_get_irq(to, 0));
+ g_assert_false(qtest_get_irq(to, 1));
+ }
+
+ qtest_quit(from);
+ qtest_quit(to);
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+
+ qtest_add_func("/mchp_pfsoc_rtc/registers", test_rtc);
+ qtest_add_func("/mchp_pfsoc_rtc/plic", test_rtc_plic);
+ qtest_add_func("/mchp_pfsoc_rtc/migration",
+ test_machine_migration);
+
+ return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index abe73370b6..3f7ecbdde7 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -305,7 +305,8 @@ qtests_riscv64 = ['riscv-csr-test'] + \
(unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
(config_all_devices.has_key('CONFIG_MICROCHIP_PFSOC') ?
['cadence-sdhci-test',
- 'mchp_pfsoc_l2cc_test'] : []) + \
+ 'mchp_pfsoc_l2cc_test',
+ 'mchp_pfsoc_rtc_test'] : []) + \
(config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and
config_all_devices.has_key('CONFIG_RISCV_IOMMU') ?
['iommu-riscv-test'] : []) + \
@@ -419,6 +420,8 @@ qtests = {
'erst-test': files('erst-test.c'),
'ivshmem-test': [rt, '../../contrib/ivshmem-server/ivshmem-server.c'],
'migration-test': test_migration_files + migration_tls_files + migration_colo_files,
+ 'mchp_pfsoc_rtc_test': files('migration/migration-qmp.c',
+ 'migration/migration-util.c'),
'pxe-test': files('boot-sector.c'),
'pnv-xive2-test': files('pnv-xive2-common.c', 'pnv-xive2-flush-sync.c',
'pnv-xive2-nvpg_bar.c'),
--
2.53.0
next prev parent reply other threads:[~2026-09-04 16:00 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 15:57 [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-09-04 15:57 ` [PATCH v2 01/24] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-09-04 15:57 ` [PATCH v2 02/24] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-09-04 15:57 ` [PATCH v2 03/24] hw/misc: pfsoc: Support DDR training with newer HSS Bin Meng
2026-09-04 15:57 ` [PATCH v2 04/24] hw/misc: pfsoc: Model L2 cache controller registers Bin Meng
2026-09-30 9:38 ` Philippe Mathieu-Daudé
2026-09-04 15:57 ` [PATCH v2 05/24] hw/riscv: pfsoc: Couple L2CC to L2-LIM Bin Meng
2026-09-30 9:38 ` Philippe Mathieu-Daudé
2026-10-03 15:10 ` Bin Meng
2026-09-04 15:57 ` [PATCH v2 06/24] tests/qtest: Add PolarFire SoC L2CC coverage Bin Meng
2026-09-04 15:57 ` [PATCH v2 07/24] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-10-04 11:14 ` Bernhard Beschow
2026-09-04 15:57 ` [PATCH v2 08/24] tests/qtest: add Cadence SDHCI ADMA pacing/MMIO reproducer Bin Meng
2026-09-04 15:57 ` [PATCH v2 09/24] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-09-30 9:25 ` Philippe Mathieu-Daudé
2026-09-04 15:57 ` [PATCH v2 10/24] hw/sd: cadence: Add 64-bit system bus property Bin Meng
2026-09-04 15:57 ` [PATCH v2 11/24] hw/riscv: pfsoc: Enable 64-bit SDHCI system bus support Bin Meng
2026-09-04 15:57 ` [PATCH v2 12/24] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-09-30 8:34 ` Conor Dooley
2026-10-03 15:10 ` Bin Meng
2026-09-04 15:57 ` [PATCH v2 13/24] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-09-04 15:57 ` [PATCH v2 14/24] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-09-04 15:57 ` Bin Meng [this message]
2026-09-04 15:57 ` [PATCH v2 16/24] hw/misc: pfsoc: Honor PolarFire service notification requests Bin Meng
2026-09-30 9:20 ` Conor Dooley
2026-10-03 15:53 ` Bin Meng
2026-09-04 15:57 ` [PATCH v2 17/24] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-09-30 9:28 ` Conor Dooley
2026-10-03 15:10 ` Bin Meng
2026-09-04 15:57 ` [PATCH v2 18/24] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-09-30 9:29 ` Conor Dooley
2026-09-04 15:57 ` [PATCH v2 19/24] hw/riscv: pfsoc: Fix Icicle Kit hart count at five Bin Meng
2026-09-30 9:33 ` Conor Dooley
2026-10-03 15:10 ` Bin Meng
2026-09-04 15:57 ` [PATCH v2 20/24] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-09-30 9:43 ` Conor Dooley
2026-10-03 15:20 ` Bin Meng
2026-09-30 10:15 ` Conor Dooley
2026-10-03 15:16 ` Bin Meng
2026-10-04 0:32 ` Conor Dooley
2026-09-04 15:57 ` [PATCH v2 21/24] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-09-04 15:57 ` [PATCH v2 22/24] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-09-04 15:57 ` [PATCH v2 23/24] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-09-04 15:57 ` [PATCH v2 24/24] MAINTAINERS: Move Conor Dooley to PolarFire SoC reviewer Bin Meng
2026-09-30 9:51 ` Conor Dooley
2026-09-04 16:11 ` [PATCH v2 00/24] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Philippe Mathieu-Daudé
2026-09-07 13:29 ` Conor Dooley
2026-09-26 3:14 ` Bin Meng
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